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ADP3421 Datasheet(PDF) 9 Page - Analog Devices |
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ADP3421 Datasheet(HTML) 9 Page - Analog Devices |
9 / 12 page REV. A ADP3421 –9– optimal compensation also gives the ripple current control that adds stability to the switching frequency. Standard Hysteretic Control Configuration The ADP3421 can also be used as a conventional hysteretic ripple regulator where the output ripple voltage is directly pro- grammed. To achieve this conventional operation, the DAC’s output is connected directly to the REG pin and the output voltage connects through a resistor to the RAMP pin. This resistor sets the output ripple voltage, which will be symmetrically centered around the DAC voltage. If the optimal DAC voltage is not available, an offset could be summed into the RAMP pin with another resistor, as was done with the previous configuration. Intel Mobile Voltage Positioning Implementation In the recommended configuration, the ADP3421 uses voltage Intel Mobile Voltage positioning technology as an inherent part of its architecture. No matter how fast the response of the switches, even instanta- neous, the inductor limits the response speed at the output of the converter. This places the primary burden of transient response containment on the output capacitors. The size and cost of the output capacitors can be minimized by keeping the output voltage higher at light load in anticipation of a load increase, and lowering the output voltage at heavier loads in anticipation of a load decrease. Voltage positioning with the ADP3421 is active, which means the voltage positioning can be controlled by loop gain. This increases efficiency compared to passive voltage positioning that is sometimes used as a supple- mentary regulation technique with voltage-mode controllers. Instead of sizing a series resistor to create the entire voltage drop (often called a “droop” resistor in the passive voltage positioning implementation), a smaller value current-sensing resistor can be used and the loop can amplify its voltage drop to position the voltage as desired without additional power loss. Voltage Positioning for Power Savings In addition to the size and cost reduction of the output capacitors, another advantage of using voltage positioning is a reduction in the CPU core dissipation. That dissipation is equal to the product of the applied core voltage and the current drawn by the CPU. The CPU current is primarily due to the capacitive switching load of digital circuitry, and it is also proportional to the applied voltage. The result is that the CPU power dissipation is approximately proportional to the applied voltage squared. PCPU = k × VCPU2 This characteristic, combined with the wide tolerance on the core voltage specification, suggests that the maximum CPU power dissipation can be substantially reduced by setting the core voltage near the lower specified voltage limit. For example, if a 1.6 V processor is operated 7% below its nominal voltage rating, the CPU power dissipation is reduced by 13.5%. Losses in the switches and inductor of the power converter are also reduced due to the decrease in maximum load current. To realize the full cost-reducing benefits of active voltage posi- tioning, a current-sensing resistor should be used to convey accurate current information to the control loop. This is needed to accurately position the core voltage as a function of load cur- rent. Accurate positioning of the core voltage allows the highest reduction in output capacitors. It is common to see passive voltage positioning implemented by sensing voltage drop on a copper trace or across a power MOSFET. This causes poor control of the voltage positioning—a tolerance analysis can show the weakness of this design technique. Although additional power is dissipated by the current-sense resistor, the total power consumption is reduced because of the squared reduction of current consumption by the CPU. For example, if the CPU draws 15 A at 1.6 V, the current-sensing resistor is 3 m Ω, and the supply voltage is reduced by 7%, the core dissipation can be reduced from 24 W to: 24 W × 0.932 = 20.76 W, and the power dissipated in the resistor is only: [20.76 W/(1.6 V × 0.93)]2 × 3 mΩ = 0.58 W. The total power savings from the battery is 2.65 W, or 11.1%. Optimally Compensated for Voltage Positioning Although voltage positioning helps to control the initial load tran- sient, high-frequency load repetition rates can cause the voltage to exceed by double the limits within which the transients can be contained. For complete transient containment over the bandwidth of the core’s transient activity, the solution is an enhanced optimally compensated version of voltage positioning. It prevents the tendency of the core voltage to “bounce” before settling to its final positioned value after the inductor current has been ramped to its final value. Main Feedback Loop Operation In conjunction with a selected control topology, the ADP3421 regulates a drive control signal at the OUT pin using a comparator. The two inputs are pins RAMP (–) and REG (+). A bidirectional switched control current is used at the RAMP input to establish hysteresis with a chosen termination resistance. Beginning in the drive high state (OUT pin high), the control current is sinking current into the RAMP pin, but the output current in the buck converter is increasing and so VRAMP will eventually exceed VREG. When this happens, the control current reverses and sources current out of the RAMP pin to provide both hysteresis and overdrive for the comparator. The OUT pin goes low and the buck converter output current decreases until VRAMP < VREG, at which time the comparator switches, the control current reverses, and the process repeats. How the hysteresis current is used (depending on the control configuration) will determine which parameter is hysteretically controlled—presumably either the inductor ripple current or the output ripple voltage, as in the two suggested configu- rations, or a weighted combination of the two or another variable could be introduced. Core Converter Design Procedure There are two primary objectives considered in optimizing the design of a power converter. The first objective is to meet the specifications; the second objective is to do so at the lowest cost. Analog Devices, Inc., addresses both of these objectives with the ADP3421 and its recommended design procedure. The optimized design yields the additional benefit of reducing the maximum CPU power consumption by ~10% for typical CPU specifica- tions, which has created great interest in those using the CPU. Microprocessors have the distinguishing characteristic of creating extremely fast load transients from nearly zero to the maximum load and vice versa. The advent of increasing power management (used to interrupt the CPU processing) causes |
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