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DP8390D Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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DP8390D Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 56 page 20 Block Diagram TLF8582 – 2 FIGURE 1 30 Functional Description (Refer to Figure 1 ) RECEIVE DESERIALIZER The Receive Deserializer is activated when the input signal Carrier Sense is asserted to allow incoming bits to be shift- ed into the shift register by the receive clock The serial receive data is also routed to the CRC generatorchecker The Receive Deserializer includes a synch detector which detects the SFD (Start of Frame Delimiter) to establish where byte boundaries within the serial bit stream are locat- ed After every eight receive clocks the byte wide data is transferred to the 16-byte FIFO and the Receive Byte Count is incremented The first six bytes after the SFD are checked for valid comparison by the Address Recognition Logic If the Address Recognition Logic does not recognize the packet the FIFO is cleared CRC GENERATORCHECKER During transmission the CRC logic generates a local CRC field for the transmitted bit sequence The CRC encodes all fields after the synch byte The CRC is shifted out MSB first following the last transmit byte During reception the CRC logic generates a CRC field from the incoming packet This local CRC is serially compared to the incoming CRC ap- pended to the end of the packet by the transmitting node If the local and received CRC match a specific pattern will be generated and decoded to indicate no data errors Trans- mission errors result in a different pattern and are detected resulting in rejection of a packet TRANSMIT SERIALIZER The Transmit Serializer reads parallel data from the FIFO and serializes it for transmission The serializer is clocked by the transmit clock generated by the Serial Network Interface (DP8391) The serial data is also shifted into the CRC gen- eratorchecker At the beginning of each transmission the Preamble and Synch Generator append 62 bits of 10 pre- amble and a 11 synch pattern After the last data byte of the packet has been serialized the 32-bit FCS field is shifted directly out of the CRC generator In the event of a collision the Preamble and Synch generator is used to generate a 32-bit JAM pattern of all 1’s ADDRESS RECOGNITION LOGIC The address recognition logic compares the Destination Ad- dress Field (first 6 bytes of the received packet) to the Phys- ical address registers stored in the Address Register Array If any one of the six bytes does not match the pre-pro- grammed physical address the Protocol Control Logic re- jects the packet All multicast destination addresses are fil- tered using a hashing technique (See register description) If the multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted otherwise it is rejected by the Proto- col Control Logic Each destination address is also checked for all 1’s which is the reserved broadcast address FIFO AND FIFO CONTROL LOGIC The NIC features a 16-byte FIFO During transmission the DMA writes data into the FIFO and the Transmit Serializer reads data from the FIFO and transmits it During reception the Receive Deserializer writes data into the FIFO and the DMA reads data from the FIFO The FIFO control logic is used to count the number of bytes in the FIFO so that after a preset level the DMA can begin a bus access and write read data tofrom the FIFO before a FIFO underflowover- flow occurs 2 |
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Similar Description - DP8390D |
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