INA+

INA-

OUTB+

INB+

INB-

OUTA+

OUTA-

OUTB-

SMBUS AND

CONTROL

VDD

24

23

22

21

20

19

11

12

8

10

9

7

VDD

AD1/EQA1

AD0/EQA0

DS64BR111

www.ti.com

SNLS343C – SEPTEMBER 2011 – REVISED APRIL 2013

Pin Diagram

(1)

The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through

multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.

DS64BR111 Pin Diagram 24 lead

PIN DESCRIPTIONS

Pin Name

Pin

Pin Description

Number

Differential High Speed I/O's

INA+, INA- ,

24, 23

I, CML

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip

INB+, INB-,

11, 12

50

Ω termination resistor connects INx+ to VDD and INx- to VDD when

enabled.

OUTA+, OUTA-,

7, 8

O,CML

Inverting and non-inverting 50

Ω driver outputs with de-emphasis. Compatible

OUTB+, OUTB-,

20, 19

with AC coupled CML inputs.

Control Pins

ENSMB

3

I, LVCMOS Float

System Management Bus (SMBus) enable pin

Tie HIGH = Register Access, SMBus Slave mode

FLOAT = SMBus Master read from External EEPROM

Tie LOW = External Pin Control Mode

ENSMB = 1 (SMBUS MODE)

SCL

5

I, LVCMOS

ENSMB Master or Slave mode

O, Open Drain

SMBUS clock input pin is enabled. A clock input in Slave mode. Can also be a

clock output in Master mode.

SDA

4

I, LVCMOS,

ENSMB Master or Slave mode

O, OPEN Drain

The SMBus bidirectional SDA pin is enabled. Data input or open drain (pull-

down only) output.

(1)

LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not specified. Unless the

"Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V mode), or VIN (in 3.3V mode). For

additional information, Table 1 Table 5

Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%

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