Z2

Z1

Z1

Z3

IOA-

IOB-

Z1

Z1

Z3

IOA+

IOB+

A

B

DS38EP100

www.ti.com

SNLS278C – JULY 2007 – REVISED APRIL 2013

Table 1. Typical Through Response

Frequency (GHz)

DS38EP100 Attenuation Typ (dB)

0.1

-7.98

0.5

-5.93

1

-3.53

1.5

-2.25

2

-1.58

3

-1.14

4

-1.26

5

-1.54

6

-1.99

7

-2.62

8

-3.26

9

-3.61

10

-4.26

Block Diagram

Figure 4. Simplified Block Diagram

APPLICATION INFORMATION

DS38EP100 DEVICE DESCRIPTION

The DS38EP100 Power-Saver equalizer is a passive network circuit composed of resistive, capacitive, and

inductive components (See Figure 4). A differential bridged T-network compensates for the transmission medium

losses and minimizes medium-induced deterministic jitter with FR4 and cables. The equalizer attenuates low

frequency signals and is a bandpass filter at the resonant frequency. The response is linear and symmetric.

I/O TERMINATIONS

The DS38EP100 I/O impedance is 100

Ω differential. The equalizer is designed for 100Ω-balanced differential

signals and is not intended for single-ended transmission.

LINEAR COMPENSATION

The unique linear compensation feature of the DS38EP100 combined with the tiny package allows maximum

flexibility in placement. The equalizer can be placed anywhere in the data path and will provide the same

compensation at the receiving circuit. (See Simplified Application Diagram)

SYMMETRIC I/O STRUCTURES

The symmetry of the passive equalization network allows bi-directional operation. Signals receive equal

compensation regardless of the direction of data flow. (See Figure 4).

Copyright © 2007–2013, Texas Instruments Incorporated

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