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DS38EP100 Datasheet(PDF) 6 Page - Texas Instruments

Part # DS38EP100
Description  DS38EP100 1 to 5 Gbps, Power-Saver Equalizer for Backplanes and Cables
Download  17 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DS38EP100 Datasheet(HTML) 6 Page - Texas Instruments

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FR4 LENGTH (in)
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0.2
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1
3.8 Gbps
Unequalized
Equalized
5 Gbps
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FR4 LENGTH (in)
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1.5 Gbps
2.5 Gbps
Equalized
Unequalized
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FR4 LENGTH (in)
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3.8 Gbps
Unequalized
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5 Gbps
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FR4 LENGTH (in)
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DS38EP100
SNLS278C – JULY 2007 – REVISED APRIL 2013
www.ti.com
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS AND NO CONNECT PADS
The differential I/Os must have a controlled differential impedance of 100
Ω. It is preferable to route all differential
lines exclusively on one layer of the board. The use of vias should be avoided if possible. If vias must be used,
they should be used sparingly and must be placed symmetrically for each side of a given differential pair.
Differential signals should be routed away from other signals and noise sources on the printed circuit board. Pin
2, Pin 5, and the center DAP have to be left as a no connect. Therefore, do not connect the landing pads of
these pins to the power or ground plane. See AN-1187 (SNOA401) for additional information on the WSON
package.
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. Residual Deterministic Jitter
Figure 6. Residual Deterministic Jitter
vs.
vs.
FR4 Length
FR4 Length
Figure 7. Eye Height
Figure 8. Eye Height
vs.
vs.
FR4 Length
FR4 Length
6
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS38EP100


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