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DS90CF364AMTD Datasheet(PDF) 10 Page - Texas Instruments |
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DS90CF364AMTD Datasheet(HTML) 10 Page - Texas Instruments |
10 / 22 page DS90CF364A, DS90CF384A SNLS040I – JUNE 2000 – REVISED APRIL 2013 www.ti.com Figure 14. DS90CF364A (Receiver) LVDS Input Strobe Position C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(1) + ISI (Inter-symbol interference)(2) Cable Skew—typically 10 ps–40 ps per foot, media dependent Cycle-to-cycle jitter is less than 250 ps at 65 MHz. ISI is dependent on interconnect length; may be zero. Figure 15. Receiver LVDS Input Skew Margin 10 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90CF364A DS90CF384A |
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