Core / CPU

Measure

I/O

Safety

B0320-03

PRE

CHG

EFCID

EFCIC

SMBus

DSG

SMBCLK

SMBDAT

SPROT

CSBAT

CSPACK

GPIO

7

Voltage

Temp

Balance

V4

P4N

P4S

XT4

V3

P3N

P3S

XT3

V2

P2N

P2S

XT2

Voltage

Temp

Balance

Voltage

Temp

Balance

Voltage

Temp

Balance

2.5VLDO

VLDO1

Watchdog

Coulomb Counter

CCBAT

CCPACK

Current A/D

RSTN

Internal

Temperature

RISC

CPU

Internal

Oscillator

Reset

Logic

and

FET Control

Second-Level

Safety

LED1–5/SEG1–5,

PSH/BP/TP,

FIELD

PowerLAN

Communication

Link

P-LAN

V1

P1N

P1S

XT1

bq78PL116

SLUSAB8B

– OCTOBER 2010 – REVISED FEBRUARY 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

Temperature is sensed by up to 4 external sensors and one on-chip sensor. This permits accurate temperature

monitoring of each cell individually. Firmware is then able to compensate for the temperature-induced effects on

capacity, impedance, and OCV on a cell-by-cell basis, resulting in superior charge/ discharge and balancing

control.

External MOSFET control inputs provide user- definable direct hardware control over MOSFET states. Smart

control prevents excessive current through MOSFET body diodes. Auxiliary inputs can be used for enhanced

safety and control in large multicell arrays.

The bq78PL116 is completely user-configurable, with parametric tables in flash memory to suit a variety of cell

chemistries, operating conditions, safety controls, and data reporting needs. It is easily configured using the

supplied bqWizard

™ graphical user interface (GUI). The device is fully programmed and requires no algorithm or

firmware development.

The bq78PL116 pin functions of LED1/SEG1

–LED5/SEG5, PSH/BP/TP, and FIELD support LED, LCD, and

electronic paper displays (EPDs). The user can configure the bq78PL116 for the desired display type.

Figure 1. BQ78PL116 Internal Block Diagram

2

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