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BQ78350DBT-R1 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ78350DBT-R1 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 32 page  bq78350-R1 SLUSCD0 – AUGUST 2015 www.ti.com SMBus Timing Specifications (continued) VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Hold time after tHD:STA 4 µs (repeated) start Repeated start setup tSU:STA 4.7 µs time tSU:STO Stop setup time 4 µs RECEIVE mode 0 tHD:DAT Data hold time TRANSMIT mode 300 ns tSU:DAT Data setup time 250 tTIMEOUT Error signal/detect See note(1) 25 35 ms tLOW Clock low period 4.7 µs tHIGH Clock high period See note(2) 4 50 Cumulative clock low tLOW:SEXT See note(3) 25 ms slave extend time Cumulative clock low tLOW:MEXT See note(4) 10 master extend time tF Clock/data fall time (VILMAX – 0.15 V) to (VIHMIN + 0.15 V) 300 ns tR Clock/data rise time 0.9 VCC to (VILMAX – 0.15 V) 1000 (1) The bq78350-R1 times out when any clock low exceeds tTIMEOUT. (2) tHIGH:MAX is minimum bus idle time. SMBC = 1 for t > 50 μs causes a reset of any transaction in progress involving the bq78350-R1. (3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to stop. (4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to stop. Figure 1. SMBus Timing Diagram 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq78350-R1 |
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