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Address

Data−In Valid

High−Z

Data Undefined (1)

WE

CE

bq4010/Y/LY

SLUS116A – MAY 1999 – REVISED JUNE 2007

-70

-85

-150

-200

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Write cycle time

70

85

150

200

Chip enable to end of write

65

75

100

150

Address valid to end of write

65

75

90

150

Measured from address valid to

Address setup time

0

0

0

0

Measured from beginning of write to

Write pulse width

55

65

90

130

Measured from WE going high to end

Write recovery time (write cycle 1)

5

5

5

5

ns

Measured from CE going high to end

Write recovery time (write cycle 2)

15

15

15

15

Measured to first low-to- high transition

Data valid to end of write

30

35

50

70

of either CE or WE.

Measured from WE going high to end

Data hold time (write cycle 1)

0

0

0

0

Measured from CE going high to end

Data hold time (write cycle 2)

0

0

0

0

Write enbled to output in high Z

0

25

0

30

0

50

0

70

Output active from end of write

5

5

5

5

(1)

A write ends at the earlier transition of CE going high and WE going high.

(2)

A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low.

(3)

(4)

(5)

If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state.

(1)

CE or WE must be high during address transition.

(2)

Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not

be applied.

(3)

If OE is high, the I/O pins remain in a state of high impedance.

Figure 8. Write Cycle No. 1 (WE-Controlled) (1)(2)(3)

9

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