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Previous Data Valid

Data Valid

Address

High−Z

High−Z

CE

bq4010/Y/LY

SLUS116A – MAY 1999 – REVISED JUNE 2007

-70

-85

-150

-200

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Read cycle time

70

85

150

200

Address access time

70

85

150

200

Chip enable access time

Output load A

70

85

150

200

Output enable to output valid

35

45

70

90

Chip enable to output in low Z

5

5

5

5

ns

Output enable to output in low Z

0

0

0

0

Output load B

Chip disable to output in high Z

0

25

0

25

0

25

0

25

Output disable to output in high Z

0

25

0

25

0

25

0

25

Output hold from address change

Output load A

10

10

10

10

(1)

WE is held high for a read cycle.

(2)

Figure 5. Read Cycle No. 1 (Address Access) (1)(2)

(1)

WE is held high for a read cycle.

(2)

(3)

Address is valid prior to or coincident with CE transition low.

Figure 6. Read Cycle No. 2 (CE Access) (1)(2)(3)

7

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