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BQ35100 Datasheet(PDF) 7 Page - Texas Instruments |
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BQ35100 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 26 page tSU(STA) SCL SDA tw(H) tw(L) tf tr t(BUF) tr td(STA) REPEATED START th(DAT) tsu(DAT) tf tsu(STOP) STOP START 7 bq35100 www.ti.com SLUSCM6A – JUNE 2016 – REVISED JULY 2016 Product Folder Links: bq35100 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics: ADC (Temperature and Voltage Measurements) (continued) TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) Specified by design. Not tested in production. tSR_CONV Conversion time Single conversion 125 ms Resolution 14 15 bits VOS(SR) Input offset 10 µV ZADC1 Effective input resistance(TS)(1) 8 MΩ ZADC2 Effective input resistance(BAT)(1) When not measuring 8 MΩ During measurement 100 KΩ ILKG(ADC) Input leakage current(1) 0.3 µA 6.12 Electrical Characteristics: Data Flash Memory TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDR Data retention(1) 10 Years Flash –programming write cycles 20,000 Cycles tWORDPROG Word programming time 2 ms ICCPROG Flash-write supply current 5 10 mA 6.13 Electrical Characteristics: I 2C-Compatible Interface Timing Characteristics TA = –40°C to 85°C, 2.45 V < VREGIN = VBAT < 5.5 V; Typical Values at TA = 25°C and VBAT = 3.6 V (unless otherwise noted) MIN NOM MAX UNIT tR SCL/SDA rise time 300 ns tF SCL/SDA fall time 300 ns tW(H) SCL pulse width (high) 600 ns tW(L) SCL pulse width (low) 1.3 µs tSU(STA) Setup for repeated start 600 ns td(STA) Start to first falling edge of SCL 600 ns tSU(DAT) Data setup time 100 ns th(DAT) Data hold time 0 ns tSU(STOP) Setup time for stop 600 ns tBUF Bus free time between stop and start 66 µs fSCL Clock frequency 400 kHz Figure 1. I2C-Compatible Interface Timing Diagrams |
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