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BQ28550DRZR-R1 Datasheet(PDF) 5 Page - Texas Instruments |
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BQ28550DRZR-R1 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 42 page Not Recommended for New Designs bq28550-R1 www.ti.com SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014 Recommended Operating Conditions (continued) TA = 25ºC, VBAT = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GPIO, SDA and SCL VIL_ –0.3 0.6 V Input voltage low GPIO, SDA and SCL VIH_ 1.2 6 V Input voltage high GPIO, SDA output VOL_ IOH = 3 mA (open drain) 0 0.4 V voltage low Capacitance for each CI SDA and SCL input capacitance 10 pF I/O pin Power Up tPUCD 250 ms Communication Delay Input voltage range VAI2 VSS – 0.25 0.25 V (SRP, SRN) 6.4 Thermal Information bq28550-R1 THERMAL METRIC(1) SON UNIT 12 PINS RθJA Junction-to-ambient thermal resistance(2) 186.4 RθJC(top) Junction-to-case(top) thermal resistance (3) 90.4 RθJB Junction-to-board thermal resistance (4) 110.7 °C/W ψJT Junction-to-top characterization parameter (5) 96.7 ψJB Junction-to-board characterization parameter (6) 90 RθJC(bottom) Junction-to-case(bottom) thermal resistance (7) n/a (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer 6.5 Electrical Characteristics: Battery Protection TA = –40 to +85ºC, VBAT =1.5 V to 5.5 V; Typical values stated, where TA = 25ºC and VBAT =3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Minimum operating VST VST = VBAT – VM 1.2 V voltage for 0 V charging Overcurrent release RSHORT VBAT = 4.0 V, VM = 1 V 30 50 100 k Ω resistance DS pin pull-down RDS VBAT = 4.0 V 6.5 13.0 26.0 k Ω resistance COUT Low Level Output VOL1 voltage (referenced to IOL = 30 µA, VBAT = 4.5 V 0.4 0.5 V VM) COUT High Level Output VOH1 voltage (referenced to IOH = 30 µA, VBAT = 4.0 V 3.4 3.7 V VM) Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: bq28550-R1 |
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