CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

GND

CDCV857

VDD

R = 60

Ω

V(CLK)

R = 60

Ω

VDD/2

V(CLK)

Figure 1. IBIS Model Output Load (used for slew rate measurement)

CDCV857A

SCOPE

C = 14 pF

VDD/2

–VDD/2

Z = 60

Ω

Z = 60

Ω

Z = 50

Ω

Z = 50

Ω

R = 10

Ω

R = 10

Ω

R = 50

Ω

V(TT)

R = 50

Ω

V(TT)

C = 14 pF

–VDD/2

–VDD/2

NOTE: V(TT)= GND

Figure 2. Output Load Test Circuit

Yx, FBOUT

Yx, FBOUT

tc(n)

tc(n+1)

tjit(cc) = tc(n) – tc(n+1)

Figure 3. Cycle-to-Cycle Jitter