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CDCM6208V2GRGZR Datasheet(PDF) 4 Page - Texas Instruments |
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CDCM6208V2GRGZR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 88 page 4 CDCM6208V2G SNAS682 – MARCH 2016 www.ti.com Product Folder Links: CDCM6208V2G Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O TYPE DESCRIPTION NAME NO. REF_SEL 6 Input LVCMOS 50kΩ pull-up Manual Reference Selection MUX for PLL. In SPI or I2C mode the reference selection is also controlled through Register 4 bit 12. REF_SEL = 0 ( ≤ VIL): selects PRI_REF REF_SEL = 1 ( ≥ VIH): selects SEC_REF (when Reg 4.12 = 1). See Table 35 for detail. ELF 41 Output Analog External loop filter pin for PLL Y0_P 14 Output Universal Output 0 Positive Terminal Y0_N 15 Output Universal Output 0 Negative Terminal Y1_P 17 Output Universal Output 1 Positive Terminal Y1_N 16 Output Universal Output 1 Negative Terminal VDD_Y0_Y1 (2 pins) 13, 18 PWR Analog Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V or 3.3 V Y2_P 20 Output Universal Output 2 Positive Terminal Y2_N 21 Output Universal Output 2 Negative Terminal Y3_P 23 Output Universal Output 3 Positive Terminal Y3_N 22 Output Universal Output 3 Negative Terminal VDD_Y2_Y3 (2 pins) 19, 24 PWR Analog Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V or 3.3 V Y4_P 26 Output Universal Output 4 Positive Terminal Y4_N 25 Output Universal Output 4 Negative Terminal VDD_Y4 27 PWR Analog Supply pin for output 4 to set between 1.8 V, 2.5 V or 3.3 V Y5_P 29 Output Universal Output 5 Positive Terminal Y5_N 28 Output Universal Output 5 Negative Terminal VDD_Y5 30 PWR Analog Supply pin for output 5 to set between 1.8 V, 2.5 V or 3.3 V Y6_P 32 Output Universal Output 6 Positive Terminal Y6_N 33 Output Universal Output 6 Negative Terminal VDD_Y6 31 PWR Analog Supply pin for output 6 to set between 1.8 V, 2.5 V or 3.3 V Y7_P 35 Output Universal Output 7 Positive Terminal Y7_N 36 Output Universal Output 7 Negative Terminal VDD_Y7 34 PWR Analog Supply pin for output 7 to set between 1.8 V, 2.5 V or 3.3 V VDD_VCO 39 PWR Analog Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The supply of this pin and the VDD_PLL2 supply pin can be combined as they are both analog and sensitive supplies VDD_PLL1 37 PWR Analog Analog Power Supply Connections VDD_PLL2 38 PWR Analog Analog Power Supply Connections; This pin is sensitive to power supply noise; The supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both power-sensitive, analog supply pins DVDD 48 PWR Analog Digital Power Supply Connections; This is also the reference supply voltage for all control inputs and must match the expected input signal swing of control inputs. GND PAD PWR Analog Power Supply Ground and Thermal Pad STATUS0 46 Output LVCMOS Status pin 0 (see Table 6 for details) STATUS1/PIN0 45 Output/ Input LVCMOS no pull resistor STATUS1: Status pin in SPI/I2C modes. For details see Table 4 for pin modes and Table 6 for status mode. PIN0: Control pin 0 in pin mode. SI_MODE1 47 Input LVCMOS 50kΩ pull-up Serial Interface Mode or Pin mode selection. SI_MODE[1:0]=00: SPI mode; SI_MODE[1:0]=01: I2C mode; SI_MODE[1:0]=10: Pin Mode (No serial programming); SI_MODE[1:0]=11: RESERVED SI_MODE0 1 Input LVCMOS 50kΩ pull-down SDI/SDA/PIN1 2 Input/ Output LVCMOS in Open drain out LVCMOS in no pull resistor SDI: SPI Serial Data Input SDA: I2C Serial Data (Read/Write bi-directional), open drain output; requires a pull- up resistor in I2C mode; PIN1: Control pin 1 in pin mode |
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