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DS110DF410 Datasheet(PDF) 7 Page - Texas Instruments |
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DS110DF410 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 61 page DS110DF410 www.ti.com SNLS397D – OCTOBER 2011 – REVISED APRIL 2015 7.5 Electrical Characteristics Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER PD Power Supply Consumption Average Power Consumption (2) 720 mW Max Transient Power Supply Current (3) 500 610 mA NTPS Supply Noise Tolerance (4) 50 Hz to 100 Hz 100 mVP-P 100 Hz to 10 MHz 40 mVP-P 10 MHz to 5.0 GHz 10 mVP-P 2.5V LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 1.75 VDD V VIH High level (ADDR[3:0] pins) 2.28 VDD VIL Low Level Input Voltage GND 0.7 V VIL Low Level Input Voltage GND 0.335 (ADDR[3:0] pins) VOH High Level Output Voltage IOH = -3mA 2.0 V VOL Low Level Output Voltage IOL = 3mA 0.4 V IIN Input Leakage Current VIN = VDD +10 μA VIN = GND -10 μA IIH Input High Current (EN_SMB pin) VIN = VDD +55 μA IIL Input Low Current (EN_SMB pin) VIN = GND -110 μA 3.3V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT) VIH High Level Input Voltage VDD = 2.5 V 1.75 3.6 V VIL Low Level Input Voltage VDD = 2.5 V GND 0.7 V VOL Low Level Output Voltage IPULLUP = 3mA 0.4 V IIH Input High Current VIN = 3.6 V, VDD = 2.5 V +20 +40 μA IIL Input Low Current VIN = GND, VDD = 2.5 V -10 +10 μA Slave Mode 100 400 fSDC SMBus clock rate kHz Master Mode(5) 400 DATA BIT RATES RB Bit Rate Range 8.5 11.3 Gbps SIGNAL DETECT SDH Signal Detect ON Threshold Level Default differential input signal level to 70 mVp-p assert signal detect, 10.3125 Gbps, PRBS-31 SDL Signal Detect OFF Threshold Default differential input signal level to de- 10 mVp-p Level assert signal detect, 10.3125 Gbps, PRBS-31 (1) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization. (2) VDD= 2.5V, TA = 25°C. All four channels active and locked. DFE powered-up and enabled. (3) Maximum power supply current during lock acquisition. All four channels active, all four channels unlocked, all registers at default settings. (4) Allowed supply noise (mVP-P sine wave) under typical conditions. (5) EEPROM device used for Master mode programming must support fSDC greater than 400kHz. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS110DF410 |
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