AD7266

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

AD7266

TOP VIEW

(Not to Scale)

1

DGND

2

REF SELECT

3

4

5

AGND

6

AGND

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

A1

23

A2

22

SGL/DIFF

21

RANGE

20

19

AGND

18

17

Figure 2. AD7266 Pin Configuration

Table 4. AD7266 Pin Function Descriptions

Pin No.

Mnemonic

Description

4, 20

Decoupling capacitors (470nF recommended) are connected to these pins to decouple the reference buffer for

each respective ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a

system. The range of the external reference is dependent on the analog input range selected. See the Reference

Configuration Options section.

7–12

Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog

input channel pairs. See Table 6.

18–13

Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog

input channel pairs. See Table 6.

27

SCLK

Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock

is also used as the clock source for the conversion process.

5, 6, 19

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any

external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to

the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not

be more than 0.3 V apart, even on a transient basis.

32

transient basis. This supply should be decoupled to DGND.

31

Logic power supply input. The voltage supplied at this pin determines at what voltage the interface will operate.

should never exceed either by more than 0.3 V.

1, 29

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should

connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis.

3

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The

transient basis. This supply should be decoupled to AGND.

26

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266

and frames the serial data transfer.

30, 28

Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are clocked out on the

falling edge of the SCLK input and 14 SCLKs are required to access the data. The data appears on both pins

simultaneously from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros

followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles

rather than 14, then two trailing zeros will appear after the 12 bits of data. If CS is held low for a further 16 SCLK

using only one serial port. See the Serial Interface section.

Rev. PrG | Page 6 of 17