50: MS

50: MS

50: MS

50: MS

L=1"

L=1"

L=1"

L=1"

L = A, B or C

100: Diff.

Stripline

DS25CP104A, DS25CP114

www.ti.com

SNLS305C – AUGUST 2008 – REVISED MARCH 2013

Figure 9. Test Channel Block Diagram

Test Channel Loss Characteristics

The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric

constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:

Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.

Test Channel

Length

Insertion Loss (dB)

(inches)

500 MHz

750 MHz

1000 MHz

1250 MHz

1500 MHz

1560 MHz

A

10

-1.2

-1.7

-2.0

-2.4

-2.7

-2.8

B

20

-2.6

-3.5

-4.1

-4.8

-5.5

-5.6

C

30

-4.3

-5.7

-7.0

-8.2

-9.4

-9.7

D

15

-1.6

-2.2

-2.7

-3.2

-3.7

-3.8

E

30

-3.4

-4.5

-5.6

-6.6

-7.7

-7.9

F

60

-7.8

-10.3

-12.4

-14.5

-16.6

-17.0

Functional Description

The DS25CP104A and DS25CP114 are 3.125 Gbps 4x4 LVDS digital crosspoint switch optimized for high-speed

signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. The

DS25CP104A and DS25CP114 operate in two modes: Pin Mode (EN_smb = 0) and SMBus Mode (EN_smb = 1).

When in the Pin Mode, the switch is fully configurable with external pins. This is possible with two input select

pins per output (e.g. S00 and S01 pins for OUT0). There is also one transmit pre-emphasis (PE) level select pin

per output for switching the PE levels between Medium and Off settings and one receive equalization (EQ) level

select pin per input for switching the EQ levels between Low and Off settings.

In the Pin Mode, feedback from the LOS (Loss Of Signal) monitor circuitry is not available (there is not an LOS

output pin).

When in the SMBus Mode, the full switch configuration, four levels of transmit pre-emphasis (Off, Low, Medium

and High), four levels of receive equalization (Off, Low, Medium and High) and SoftPWDN can be programmed

via the SMBus interface. In addition, by using the SMBus interface, a user can obtain the feedback from the built-

in LOS circuitry which detects an open inputs fault condition.

In the SMBus Mode, the S00 and S01 pins become SMBus clock (SCL) input and data (SDA) input pins

respectively; the S10, S11, S21 and S21 pins become the User-Set SMBus Slave Address input pins (ADDR0, 1,

2 and 3) while the S30 and S31 pins become non-functional (tieing these two pins to either H or L is

recommended if the device will function only in the SMBus mode).

In the SMBus Mode, the PE and EQ select pins as well as the PWDN pin remain functional. How these pins

function in each mode is explained in the following sections.

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