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DS22EV5110 Datasheet(PDF) 8 Page - Texas Instruments |
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DS22EV5110 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 23 page tSL LOCK SD 50% 50% tDD, tCD OUT IN 0V 0V 0V 20% 80% 80% 20% OUT+ OUT- VO = (OUT+) ± (OUT-) tF tR DS22EV5110 SNLS311E – APRIL 2009 – REVISED APRIL 2013 www.ti.com Figure 3. CML Output Transition Times Figure 4. CML Latency Delay Time Figure 5. SD – LOCK Delay Time 8 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: DS22EV5110 |
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