DS15BR400, DS15BR401

www.ti.com

SNLS224G – AUGUST 2006 – REVISED APRIL 2013

PIN DESCRIPTIONS (continued)

Pin

TQFP Pin

WQFN Pin

I/O, Type

Description

Name

Number

Number

DIFFERENTIAL OUTPUTS

OUT0+

48

32

O, LVDS

OUT0

−

47

31

OUT1+

46

30

O, LVDS

OUT1

−

45

29

OUT2+

42

28

O, LVDS

OUT2

−

41

27

OUT3+

40

26

O, LVDS

OUT3-

39

25

DIGITAL CONTROL INTERFACE

PWDN

12

8

I, LVTTL

A logic low at PWDN activates the hardware power down mode (all channels).

PEM

2

2

I, LVTTL

Pre-emphasis Control Input (affects all Channels)

POWER

3, 4, 5, 7, 10,

3, 4, 6, 7, 20,

I, Power

11, 28, 29, 32,

21

33

GND

8, 9, 17, 18, 23,

I, Ground

Ground reference for LVDS and CMOS circuitry. For the WQFN package, the

24, 37, 38, 43,

DAP is used as the primary GND connection to the device in addition to the pin

44

numbers listed. The DAP is the exposed metal contact at the bottom of the

WQFN-32 package. It should be connected to the ground plane with at least 4

vias for optimal AC and thermal performance.

N/C

1,6, 25, 26, 27,

1, 17,

No Connect

30, 31, 34, 35,

18,19,22, 23,

36

24

(1)

The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and

DS15BR401 are optimized for point-to-point backplane and cable applications.

(2)

Note that for the WQFN package the GND is connected thru the DAP on the back side of the WQFN package in addition to the actual

pin numbers listed.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2006–2013, Texas Instruments Incorporated

Submit Documentation Feedback

3

Product Folder Links: DS15BR400 DS15BR401