CDC330

CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS329A – OCTOBER 1993 – REVISED MARCH 1994

2–4

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

MIN

MAX

UNIT

f lk

Clock frequency

1A/3A (duty cycle 40 – 60%)

67

MHz

fclock

Clock frequency

2A (duty cycle 40 – 60%)

100

MHz

1A/3A low

5.9

1A/3A high

5.9

tw

Pulse duration

2A low

2.8

ns

2A high

4.5

PRE low

3

tsu

Setup time

PRE inactive before 2A

↓

2

ns

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Note 4 and Figures 1 and 2)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN

MAX

UNIT

f

†

1A or 3A

Any 1Y or 3Y

67

MHz

fmax†

2A

Any Q

100

MHz

tPLH

An AorA

AnyYorQ

11

ns

tPHL

Any A or A

Any Y or Q

10.5

ns

tPHL

PRE

Any Q

12.5

ns

tPZH

An OE

AnyYorQ

9

ns

tPZL

Any OE

Any Y or Q

8.5

ns

tPHZ

An OE

AnyYorQ

8.5

ns

tPLZ

Any OE

Any Y or Q

9

ns

1A

Any 1Y

0.4

t k( )

3A

Any 3Y

0.4

ns

tsk(o)

1A or 3A

Any 1Y or 3Y

0.5

ns

2A

Any Q

0.4

tsk(pr)

Any A or A

Any Y or Q

1

ns

† Duty cycle 40 – 60%

NOTE 4: All specifications are valid only for all outputs switching.