CDCEL937QPWRQ1 datasheet(7/30 Pages) TI1

Part #	CDCEL937QPWRQ1

Description	PROGRAMMABLE 3-PLL VCXO CLOCK SYNTHESIZER

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CDCE937-Q1

CDCEL937-Q1

www.ti.com

SCAS892B – FEBRUARY 2010 – REVISED MAY 2010

DEVICE CHARACTERISTICS (continued)

over recommended operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

LVCMOS PARAMETER for Vddout = 2.5 V (CDCE937)

Vddout = 2.3 V, IOH = –0.1 mA

2.2

VOH

LVCMOS high-level output voltage

Vddout = 2.3 V, IOH = –6 mA

1.7

V

Vddout = 2.3 V, IOH = –10 mA

1.6

Vddout = 2.3 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

Vddout = 2.3 V, IOL = 6 mA

0.5

V

Vddout = 2.3 V, IOL = 10 mA

0.7

tPLH,

Propagation delay

All PLL bypass

3.4

ns

tPHL

tr/tf

Rise and fall time

Vddout = 2.5 V (20%–80%)

0.8

ns

1 PLL switching, Y2-to-Y3

60

90

tjit(cc)

Cycle-to-cycle jitter(6) (7)

ps

3 PLL switching, Y2-to-Y7

100

150

1 PLL switching, Y2-to-Y3

70

100

tjit(per)

Peak-to-peak period jitter(8)

ps

3 PLL switching, Y2-to-Y7

120

180

fOUT = 50 MHz; Y1-to-Y3

60

tsk(o)

Output skew(8), See Table 2

ps

fOUT = 50 MHz; Y2-to-Y5

160

odc

Output duty cycle(9)

f(VCO) = 100 MHz; Pdiv = 1

45%

55%

LVCMOS PARAMETER for Vddout = 1.8 V (CDCEL937)

Vddout = 1.7 V, IOH = –0.1 mA

1.6

VOH

LVCMOS high-level output voltage

Vddout = 1.7 V, IOH = –4 mA

1.4

V

Vddout = 1.7 V, IOH = –8 mA

1.1

Vddout = 1.7 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

Vddout = 1.7 V, IOL = 4 mA

0.3

V

Vddout = 1.7 V, IOL = 8 mA

0.6

tPLH,

Propagation delay

All PLL bypass

2.6

ns

tPHL

tr/tf

Rise and fall time

Vddout= 1.8 V (20%–80%)

0.7

ns

1 PLL switching, Y2-to-Y3

70

120

tjit(cc)

Cycle-to-cycle jitter(6) (7)

ps

3 PLL switching, Y2-to-Y7

100

150

1 PLL switching, Y2-to-Y3

90

140

ps

tjit(per)

Peak-to-peak period jitter(7)

3 PLL switching, Y2-to-Y7

120

190

fOUT = 50 MHz; Y1-to-Y3

60

tsk(o)

Output skew(8), See Table 2

ps

fOUT = 50 MHz; Y2-to-Y5

160

odc

Output duty cycle(9)

f(VCO) = 100 MHz; Pdiv = 1

45%

55%

SDA/SCL PARAMETER

VIK

SCL and SDA input clamp voltage

VDD = 1.7 V; II = –18 mA

–1.2

V

IIH

SCL and SDA input current

VI = VDD; VDD = 1.9 V

±10

mA

VIH

SDA/SCL input high voltage(10)

0.7 VDD

V

VIL

SDA/SCL input low voltage(10)

0.3 VDD

V

VOL

SDA low-level output voltage

IOL = 3 mA, VDD = 1.7 V

0.2 VDD

V

CI

SCL/SDA Input capacitance

VI = 0 V or VDD

3

10

pF

(6)

10000 cycles.

(7)

Jitter depends on configuration. Data is taken under the following conditions: 1-PLL : fIN = 27MHz, Y2/3 = 27 MHz, (measured at Y2),

3-PLL: fIN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz

(8)

The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data

taking on rising edge (tr).

(9)

odc depends on output rise and fall time (tr/tf).

(10) SDA and SCL pins are 3.3 V tolerant.

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