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CDC2510B Datasheet(PDF) 8 Page - Texas Instruments

Part # CDC2510B
Description  3.3V Phase-Lock Loop Clock Driver
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDC2510B Datasheet(HTML) 8 Page - Texas Instruments

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CDC2510B
3.3V PHASELOCK LOOP CLOCK DRIVER
SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
PHASE ERROR
vs
SUPPLY VOLTAGE
300
250
150
100
50
0
200
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
350
400
−50
−100
fc = 100 MHz
CLY = CLF = 30 pF
TA = 25°C
Phase Error Measured
from CLK to FBIN
VCC − Supply Voltage − V
Figure 6
JITTER
vs
CLOCK FREQUENCY
400
300
250
200
0
350
35
45
55
65
75
85
95
105 115 125
150
100
50
Cycle to Cycle
Peak to Peak
VCC = 3.3 V
TA = 25°C
fc − Clock Frequency − MHz
Figure 7
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
12
10
6
4
2
0
8
10
20
40
60
80
100
120
140
14
16
AVCC = 3.6 V
Bias = 0/3 V
CLY = CLF = 30 pF
TA = 25°C
fc − Clock Frequency − MHz
Figure 8
0
50
100
150
200
250
20
40
60
80
100
120
140
SUPPLY CURRENT
vs
CLOCK FREQUENCY
fclk − Clock Frequency − MHz
VCC = 3.6 V
TA = 25°C
CLY = CLF = 30 pF
NOTES: A. CLY = Lumped capacitive load at Y
B. CLF = Lumped feedback capacitance at FBIN


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