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A8904SLB Datasheet(PDF) 7 Page - Allegro MicroSystems

Part # A8904SLB
Description  3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A8904SLB Datasheet(HTML) 7 Page - Allegro MicroSystems

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8904
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
www.allegromicro.com
7
Terminal Functions
A8904SLB
A8904SLP
Terminal Name
Function
(SOIC)
(HTSSOP)
LOAD SUPPLY
V
BB; the 5 V or 12 V motor supply.
1
15
C
D2
One of two capacitors used to generate the ideal commutation points from
2
16
the back-EMF zero crossing points.
C
WD
Timing capacitor used by the watchdog circuit to blank out the back-EMF
3
17
comparators during commutation transients, and to detect incorrect motor
position.
C
ST
Startup oscillator timing capacitor.
4
18
NC
No( internal) connection.
19
OUT
A
Power amplifier A output to motor.
5
20
NC
No (internal) connection.
21
GROUND
Power and logic ground and thermal heat sink.
6-7
POWER GROUND
Power ground.
22*
NC
No (internal) connection.
23
OUT
B
Power amplifier B output to motor.
8
24
OUT
C
Power amplifier C output to motor.
9
25
CENTERTAP
Motor centertap connection for back-EMF detection circuitry.
10
26
BRAKE
Active low turns ON all three sink drivers shorting the motor windings to
11
27
ground. External capacitor and resistor at BRAKE provide brake delay.
The brake function can also be controlled via the serial port.
C
RES
External reservoir capacitor used to hold charge to drive the source drivers’
12
28
gates. Also provides power for brake circuit.
ANALOG GROUND
Analog ground.
1*
FILTER
Analog voltage input/output to control motor current. Also, compensation node
for internal speed control loop.
13
2
SECTOR DATA
External tachometer input. Can use sector or index pulses from disk to
14
3
provide precise motor speed feedback to internal frequency-locked loop.
LOGIC SUPPLY
V
DD; the 5 V logic supply.
15
4
OSCILLATOR
Clock input for the speed reference counter.
16
5
DATA OUT
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in
17
6
real time, controlled by 2-bit multiplexer via serial port.
NC
No (internal) connection.
7
GROUND
Power and logic ground and thermal heat sink.
18-19
DIGITAL GROUND
Logic ground.
–8*
RESET
When pulled low forces the chip into sleep mode; clears all serial port bits.
20
9
NC
No (internal) connection.
10
CHIP SELECT
Strobe input (active low) for data word.
21
11
CLOCK
Clock input for serial port.
22
12
DATA IN
Sequential data input for the serial port.
23
13
C
D1
One of two capacitors used to generate the ideal commutation points from
24
14
the back-EMF zero crossing points.
* For the A8904SLP, ground terminals 1, 8, and 22 must be connected together externally.


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