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DP83850CVF Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DP83850CVF Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 37 page © 1998 National Semiconductor Corporation www.national.com June 1998 DP83850C 100 Mb/s TX/T4 Repeater Interface Controller (100RIC™) General Description The DP83850C 100 Mb/s TX/T4 Repeater Interface Con- troller, known as 100RIC, is designed specifically to meet the needs of today's high speed Ethernet networking sys- tems. The DP83850C is fully compatible with the IEEE 802.3 repeater's clause 27. The DP83850C supports up to twelve 100 Mb/s links with its network interface ports. The 100RIC can be configured to be used with either 100BASE-TX or 100BASE-T4 PHY technologies. Larger repeaters with up to 372 ports may be constructed by cascading DP83850Cs together using the built-in Inter Repeater bus. In conjunction with a DP83856 100 Mb/s Repeater Infor- mation Base device, a DP83850C based repeater becomes a managed entity that is compatible with IEEE 802.3u (clause 30), collecting and providing an easy inter- face to all the required network statistics. System Diagram FAST® is a registered trademark of Fairchild Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. 100RIC ™ is a trademark of National Semiconductor Corporation. Note: The above system diagram depicts the repeater configured in 100BASE-TX mode. DP83856 100 Mb/s Repeater Information Base (100RIB) DP83223 100BASE-X Transceiver Port 0 100Mb/s Ethernet Ports Inter Repeater Bus RX Enable [11..0] Management Bus MII DP83850C 100 Mb/s Repeater Interface Controller (100RIC8) Management I/O Devices Program Memory Management CPU Statistics SRAM DP83840A 100 PHY #0 DP83223 100BASE-X Transceiver Port 1 DP83840A 100 PHY #1 DP83223 100BASE-X Transceiver Port 2 DP83840A 100 PHY #2 DP83223 100BASE-X Transceiver Port 11 DP83840A 100 PHY #11 (IR_COL, IR_DV) Features s IEEE 802.3u repeater and management compatible s Supports Class II TX translational repeater and Class I T4 repeater s Supports 12 network connections (ports) s Up to 31 repeater chips cascadable for larger hub appli- cations (up to 372 ports) s Separate jabber and partition state machines for each port s Management interface to DP83856 allows all repeater MIBs to be maintained s Large per-port management counters - reduces man- agement CPU overhead s On-chip elasticity buffer for PHY signal re-timing to the DP83850C clock source s Serial register interface - reduces cost s Physical layer device control/status access available via the serial register interface s Detects repeater identification errors s 132 pin PQFP package |
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