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DAC8228SRTQR Datasheet(PDF) 7 Page - Texas Instruments |
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DAC8228SRTQR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 55 page  DAC8228 www.ti.com SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS: Single-Supply All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted. DAC8228 PARAMETER CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Resolution 14 Bits Linearity error Measured by line passing through codes 0040h and 3FFFh ±1 LSB Differential linearity error Measured by line passing through codes 0040h and 3FFFh ±1 LSB TA = +25°C, before user calibration, gain = 6, code = 0040h ±2.5 LSB Unipolar zero error TA = +25°C, before user calibration, gain = 4, code = 0040h ±4 LSB TA = +25°C, after user calib., gain = 4 or 6, code = 0040h ±1 LSB Unipolar zero error TC Gain = 4 or 6, code = 0040h ±0.5 ±3 ppm FSR/°C TA = +25°C, gain = 6 ±2.5 LSB Gain error TA = +25°C, gain = 4 ±4 LSB Gain error TC Gain = 4 or 6 ±1 ±3 ppm FSR/°C TA = +25°C, before user calibration, gain = 6, code = 3FFFh ±2.5 LSB Full-scale error TA = +25°C, before user calibration, gain = 4, code = 3FFFh ±4 LSB TA = +25°C, after user calib., gain = 4 or 6, code = 3FFFh ±1 LSB Full-scale error TC Gain = 4 or 6, code = 3FFFh ±0.5 ±3 ppm FSR/°C Measured channel at code = 2000h, full-scale change on any DC crosstalk(1) 0.05 LSB other channel ANALOG OUTPUT (VOUT-0 to VOUT-7) (2) VREF = +5V 0 +30 V Voltage output(3) VREF = +1.5V 0 +9 V Output impedance Code = 2000h 0.5 Ω Short-circuit current(4) ±10 mA Load current See Figure 89 and Figure 90 ±3 mA TA = +25°C, Device operating for 500 hours, full-scale output 3.4 ppm of FSR Output drift vs time TA = +25°C, Device operating for 1000 hours, full-scale output 4.3 ppm of FSR Capacitive load stability 500 pF To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 0040h to 10 μs 3FFFh and 3FFFh to 0040h To 1 LSB, CL = 200pF, RL = 10kΩ, code from 0040h to 3FFFh Settling time 15 μs and 3FFFh to 0040h To 1 LSB, CL = 200pF, RL = 10kΩ, code from 1F00h to 2100h 6 μs and 2100h to 1F00h Slew rate(5) 6 V/ μs Power-on delay(6) From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low 200 μs Power-down recovery time 50 μs Digital-to-analog glitch(7) Code from 1FFFh to 2000h and 2000h to 1FFFh 4 nV-s Glitch impulse peak amplitude Code from 1FFFh to 2000h and 2000h to 1FFFh 5 mV (1) The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk. (2) Specified by design. (3) The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF) for gain = 6. The maximum value of the analog output must not be greater than (AVDD – 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted. (4) When the output current is greater than the specification, the current is clamped at the specified maximum value. (5) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale. (6) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid digital communication. (7) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 1FFFh and 2000h in straight binary format. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): DAC8228 |
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