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DP83848SKGD1 Datasheet(PDF) 10 Page - Texas Instruments |
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DP83848SKGD1 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 81 page TX_CLK TX_EN TXD PMD output pair (J/K) T2.6.1 IDLE DATA RX_CLK RXD[3:0] RX_DV RX_ER Valid data T2.5.2 T2.5.1 T2.5.1 DP83848-HT SLLSEJ7 – FEBRUARY 2015 www.ti.com Table 5. 100 Mb/s MII Receive Timing PARAMETER NOTES MIN TYP MAX UNIT T2.5.1 RX_CLK high/low time 100 Mb/s normal mode 13 20 24 ns T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER delay 100 Mb/s normal mode 20 ns Figure 5. 100 Mb/s MII Receive Timing Table 6. 100BASE-TX Transmit Packet Latency Timing PARAMETER NOTES(1) MIN TYP MAX UNIT T2.6.1 TX_CLK to PMD output pair latency 100 Mb/s normal mode 6 bits (1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode. Figure 6. 100BASE-TX Transmit Packet Latency Timing 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DP83848-HT |
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