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DP83822HFRHBR Datasheet(PDF) 3 Page - Texas Instruments |
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DP83822HFRHBR Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 47 page  3 DP83822HF, DP83822IF, DP83822H, DP83822I www.ti.com SNLS505 – JULY 2016 Product Folder Links: DP83822HF DP83822IF DP83822H DP83822I Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 5 Detailed Description 5.1 Register Maps In the register definitions under the “TYPE” heading, the following definitions apply: COR Clear on Read Strap Default value loads from strapping pin after reset LH Latched high and held until read LL Latched low and held until read RO Read Only Access RO/COR Read Only, Clear on Read RO/P Read Only, Permanently set to a default value RW Read Write access RW/SC Read Write access, Self Clearing bit SC Register sets on event occurrence and Self-Clears when event ends Table 1. 0x0000 Basic Mode Control Register (BMCR) BIT NAME TYPE DEFAULT FUNCTION 15 Reset RW, SC 0 PHY Software Reset: 1 = Initiate software Reset / Reset in Progress 0 = Normal Operation Writing a 1 to this bit resets the PHY PCS registers. When the reset operation is done, this bit is cleared to 0 automatically. PHY Vendor Specific registers will not be cleared. 14 MII Loopback RW 0 MII Loopback: 1 = MII Loopback enabled 0 = Normal Operation When MII loopback mode is activated, the transmitted data presented on MII TXD is looped back to MII RXD internally. 13 Speed Selection RW, Strap 1 Speed Select: 1 = 100 Mbps 0 = 10 Mbps When Auto-Negotiation is disabled (bit[12] = 0 in Register 0x0000), writing to this bit allows the port speed to be selected. 12 Auto-Negotiation Enable RW, Strap 1 Auto-Negotiation Enable: 1 = Enable Auto-Negotiation 0 = Disable Auto-Negotiation If Auto-Negotiation is disabled, bit[8] and bit[13] of this register determine the port speed and duplex mode. 11 IEEE Power Down RW 0 Power Down: 1 = IEEE Power Down 0 = Normal Operation The PHY is powered down after this bit is set. Only register access is enabled during this power down condition. To control the power down mechanism, this bit is OR'ed with the input from the INT/PWDN_N pin. When the active low INT/PWDN_N is asserted, this bit is set. 10 Isolate RW 0 Isolate: 1 = Isolates the port from the MII with the exception of the SMI 0 = Normal Operation |
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