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DLPA2000 Datasheet(PDF) 7 Page - Texas Instruments |
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DLPA2000 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 41 page 7 DLP2010 www.ti.com DLPS046B – JULY 2014 – REVISED JULY 2016 Product Folder Links: DLP2010 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V (1) Recommended Operating Conditions are applicable after the DMD is installed in the final product. (2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits. (3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET. (4) All voltage values are with respect to the ground pins (VSS). (5) VOFFSET supply transients must fall within specified max voltages. (6) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit. (7) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. (8) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit. (9) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands. (10) Refer to the SubLVDS timing requirements in Timing Requirements. 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN NOM MAX UNIT SUPPLY VOLTAGE RANGE(4) VDD Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface 1.65 1.8 1.95 V VDDI Supply voltage for SubLVDS receivers 1.65 1.8 1.95 V VOFFSET Supply voltage for HVCMOS and micromirror electrode(5) 9.5 10 10.5 V VBIAS Supply voltage for mirror electrode 17.5 18 18.5 V VRESET Supply voltage for micromirror electrode –14.5 –14 –13.5 V |VDDI–VDD| Supply voltage delta (absolute value)(6) 0.3 V |VBIAS–VOFFSET| Supply voltage delta (absolute value)(7) 10.5 V |VBIAS–VRESET| Supply voltage delta (absolute value)(8) 33 V CLOCK FREQUENCY ƒclock Clock frequency for low speed interface LS_CLK(9) 108 120 MHz ƒclock Clock frequency for high speed interface DCLK(10) 300 600 MHz Duty cycle distortion DCLK 44% 56% SUBLVDS INTERFACE (10) | VID | SubLVDS input differential voltage (absolute value) Figure 8, Figure 9 150 250 350 mV VCM Common mode voltage Figure 8, Figure 9 700 900 1100 mV VSUBLVDS SubLVDS voltage Figure 8, Figure 9 575 1225 mV ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω ZIN Internal differential termination resistance Figure 10 80 100 120 Ω 100-Ω differential PCB trace 6.35 152.4 mm |
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