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DAC7731EC1K Datasheet(PDF) 4 Page - Texas Instruments |
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DAC7731EC1K Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 22 page  DAC7731 4 SBAS249B www.ti.com PARAMETER DESCRIPTION MIN TYP MAX UNITS tWH SCLK HIGH Time 25 ns tWL SCLK LOW Time 25 ns tSDI Setup Time: Data in valid before rising SCLK 5 ns tHDI Hold Time: Data in valid after rising SCLK 20 ns tSCS Setup Time: CS falling edge before first rising SCLK 15 ns tHSC Hold Time: CS rising edge after 16th rising SCLK 0 ns tDDO Delay Time: CS Falling Edge to Data Out valid, CL = 20pF on SDO 50 ns tHDO Hold Time: Data Out valid after SCLK rising edge, CL 20pF on SDO 50 ns tDDOZ Delay Time: CS rising edge to SDO = High Impedance 70 ns tWCSH CS HIGH Time 50 ns tWLDL LDAC LOW Time 20 ns tWLDH LDAC HIGH Time 20 ns tSLD Setup Time: 16th Rising SCLK Before LDAC Rising Edge 15 ns tDLD Delay Time: LDAC rising edge to first SCLK rising edge of next 15 ns transfer cycle. tSCLK Setup Time: CS High before falling SCLK edge following 16th 5 ns rising SCLK edge tSRS Setup Time: RSTSEL Valid Before RST LOW 0 ns tHRS Hold Time: RSTSEL valid after RST HIGH 20 ns tWRL RST LOW Time 30 ns tS DAC VOUT Settling Time 5 µs TIMING CHARACTERISTICS VCC = +15V, VSS = –15V, VDD = 5V; RL = 2kΩ to AGND; CL = 200pF to AGND; all specifications –40°C to +85°C, unless otherwise noted. DAC7731 CS SCLK SDI SDO LDAC V OUT t SCS t HCS t WH t WL t SCLK t HDI t SDI t DDO t HDO t DDOZ t WLDL t DLD t SLD t S t WLDH t WCSH 12 16 B15 B14 B13 B0 A15 A14 A13 A0 C15 C14 C13 C12 B15 B14 B13 B12 Word B Word A Word C Word B ±0.003% of FSR Error Bands RSTSEL (RSTSEL = LOW) (RSTSEL = HIGH) RST V OUT V OUT t SRS t HRS t WRL t S +FS +FS –FS –FS Min-Scale Mid-Scale INTERFACE TIMING RESET TIMING |
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