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74LVCH16901DGGRE4 Datasheet(PDF) 7 Page - Texas Instruments |
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74LVCH16901DGGRE4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 13 page www.ti.com Timing Requirements Switching Characteristics SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145C – OCTOBER 1998 – REVISED JUNE 2005 over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V(1) VCC = 2.7 V ± 0.2 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency 125 125 125 125 MHz CLK ↑ 4 3 3 3 tw Pulse duration ns LE high 3 3 3 3 A, APAR or B, BPAR before CLK ↑ 4.7 2.7 2.8 2.5 tsu Setup time CLKEN before CLK ↑ 4.5 2.9 2.9 2.5 ns A, APAR or B, BPAR before LE ↓ 0 2.2 2.1 2 A, APAR or B, BPAR after CLK ↑ 0 1.2 1.2 1.3 th Hold time CLKEN after CLK ↑ 0 1.3 1.3 1.5 ns A, APAR or B, BPAR after LE ↓ 1 1.7 1.9 1.7 (1) Texas Instruments SPICE simulation data over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V(1) VCC = 2.7 V FROM TO ± 0.2 V ± 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN TYP MIN MAX MIN MAX MIN MAX fmax 125 125 125 125 MHz B or A 5.9 1 6.2 5.8 1 5.4 A or B BPAR or APAR 12.7 2 9.9 8.6 2 7.7 BPAR or APAR 7 1 6.7 6.2 1 5.7 APAR or BPAR ERRA or ERRB 13 2 10.7 9.7 2 8.5 ERRA or ERRB 9.9 1.5 9.7 8.9 1.5 7.8 ODD/EVEN BPAR or APAR 10.4 1.5 9.3 8.6 1.5 7.5 SEL BPAR or APAR 6.9 1 7.1 6.9 1 6.1 A or B 6.9 1 7.4 6.8 1 6.1 BPAR or APAR 8.5 1.5 8.1 7.3 1.5 6.6 tpd ns parity feedthrough CLKAB or CLKBA BPAR or APAR 14.1 2.5 11.2 9.7 2 8.7 parity generated ERRA or ERRB 14.3 2.5 11.5 9.9 2 8.9 A or B 6.8 1 7 6.5 1 5.8 BPAR or APAR 7.9 1.5 7.7 7 1.5 6.3 parity feedthrough LEAB or LEBA BPAR or APAR 13.6 2.5 10.8 9.3 2 8.4 parity generated ERRA or ERRB 13.5 2.5 10.9 9.5 2 8.5 ten OEAB or OEBA B, BPAR or A, APAR 6.8 1.4 7.3 7.1 1 6.3 ns tdis OEAB or OEBA B, BPAR or A, APAR 6.9 1.3 7.1 6.2 1.5 5.9 ns ten OEAB or OEBA ERRA or ERRB 7.4 1.4 7.2 6.5 1 5.9 ns tdis OEAB or OEBA ERRA or ERRB 9.3 1.3 8.3 7.5 1 6.7 ns ten SEL ERRA or ERRB 7.6 1.4 7.7 7.5 1 6.5 ns tdis SEL ERRA or ERRB 7.8 1.3 7.4 6.4 1.5 5.9 ns (1) Texas Instruments SPICE simulation data 7 Not Recommended For New Designs |
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