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1D

C1

CLK

1D

C1

CLK

1B1

1OEAB

1CLKAB

1LEAB

1LEBA

1CLKBA

1OEBA

1A1

B3

A4

A3

K3

J4

J3

A2

A5

To 17 Other Channels

SN74ALVCH32501

36-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES144G – OCTOBER 1998 – REVISED OCTOBER 2004

INPUTS

OUTPUT

B

OEAB

LEAB

CLKAB

A

L

X

X

X

Z

H

H

X

L

L

H

H

X

H

H

H

L

↑

L

L

H

L

↑

H

H

H

L

H

X

H

L

L

X

(1)

A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA,

LEBA, and CLKBA.

(2)

Output level before the indicated steady-state input conditions were

established, provided that CLKAB was high before LEAB went low

(3)

Output level before the indicated steady-state input conditions were

established

LOGIC DIAGRAM (POSITIVE LOGIC)

3