bq26231

SLUS491 – JULY 2001

9

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APPLICATION INFORMATION

CLEAR register

The host system is responsible for register maintenance. To facilitate this maintenance, the bq26231 has a clear

register (TMP/CLR) designed to reset the specific counter or register pair to zero. The host system clears a

register by writing the corresponding register bit to 1. When the bq26231 completes the reset, the corresponding

bit in the TMP/CLR register is automatically reset to 0, which saves the host an extra write/read cycle. Clearing

the DTC register clears the STD bit and sets the DTC count rate to the default value of 1 count per 0.8789 s.

Clearing the CTC register clears the STC bit and sets the CTC count rate to the default value of 1 count per

0.8789 s.

calibration mode

to 1. The bq26231 then enters calibration mode when the HDQ line is low for greater than 10 seconds and when

CAUTION:

Ensure that no low-level external signal is present between SR1 and SR2, because it affects the

calibration value that the bq26231 calculates.

the OFR register, and the calibration bit is reset to zero, indicating to the system that the calibration cycle is

complete. Once calibration is complete, the bq26231 enters a low-power mode until HDQ goes high, indicating

cycle until the conditions are met. The calibration bit does not reset to zero until a valid calibration cycle is

completed. The requirement for HDQ to remain low for the calibration cycle can be disabled by setting the

at the end of a valid calibration cycle.

communicating with the bq26231

The bq26231 includes a simple single-wire (referenced to VSS) serial data interface. A host processor uses the

interface to access various bq26231 registers.

NOTE:

The HDQ pin requires an external pullup or pulldown resistor.

The interface uses a command-based protocol, where the host processor sends a command byte to the

bq26231. The command directs the bq26231 either to store the next eight bits of data received to a register

specified by the command byte or to output the eight bits of data from a register specified by the command byte.

The communication protocol is asynchronous return-to-one. Command and data bytes consist of a stream of

eight bits that have a maximum transmission rate of 5K bits/s. The least-significant bit of a command or data

byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using

either polled or interrupt processing. Data input from the bq26231 may be sampled using the pulse-width

capture timers available on some microcontrollers. A UART may also be used to communicate through the HDQ

pin.

this is the first access command), then a break should be sent by the host. The host may then resend the

receive a command from the host processor.

Not Recommended for New Designs