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BQ24250CYFFT Datasheet(PDF) 4 Page - Texas Instruments |
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BQ24250CYFFT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 48 page  bq24250C F 1 IN IN BOOT ILIM E D SW SW /CE INT 2 PGND PGND EN1 TS 3 PMID STAT EN2 SCL 4 SYS SYS ISET LDO 5 BAT BAT PGND SDA B VDPM IN SW PGND SYS BAT A C bq24250C SLUSBY7 – JULY 2014 www.ti.com 6 Pin Configuration and Functions YFF Package (30-Ball 2.4 mm × 2 mm DSBGA) Top View Pin Descriptions PIN bq24250C bq24250C I/O DESCRIPTION NAME YFF RGE Analog Ground for QFN only. Connect to the thermal pad and the ground plane AGND – 4 of the circuit. Battery Connection. Connect to the positive pin of the battery. Additionally, BAT A1, B1, C1 11–12 I/O bypass BAT with a >1 μF capacitor. High Side MOSFET Gate Driver Supply. Connect a 0.033 μF ceramic capacitor BOOT E5 21 I (voltage rating > 15V) from BOOT to SW to supply the gate drive for the high side MOSFETs. Charge Enable Active-Low Input. Connect CE to a high logic level to place the CE D4 1 I battery charger in standby mode. Charge Status Open Drain Output. CHG is pulled low when a charge cycle starts and remains low while charging. CHG is high impedance when the CHG – – O charging terminates and when no supply exists. CHG does not indicate recharge cycles. EN1 D3 2 I Input Current Limit Configuration Inputs. Use EN1, and EN2 to control the maximum input current and enable USB compliance. See Table 1 for EN2 D2 3 I programming details. Input Current Limit Programming Input. Connect a resistor from ILIM to GND to program the input current limit for IN. The current limit is programmable from ILIM F5 22 I 0.5A to 2A. ILIM has no effect on the USB input. If an external resistor is not desired, short to GND for a 2A default setting. Input power supply. IN is connected to the external DC supply (AC adapter or IN A5,B5,C5 19 I USB port). Bypass IN to PGND with >2 μF ceramic capacitor Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during charging. INT is high impedance when charging is complete or the charger is disabled. When a fault occurs, a 256 μs INT E1 8 O pulse is sent out as an interrupt for the host. INT will indicate recharge cycles. Connect INT to a logic rail through a 10k Ω resistor to communicate with the host processor. 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: bq24250C |
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