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BQ24187YFFT Datasheet(PDF) 9 Page - Texas Instruments |
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BQ24187YFFT Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 44 page  bq24187 www.ti.com SLUSBM0 – APRIL 2014 7.6 Timing Requirements Circuit of Figure 6, VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = –40°C–125°C and TJ=25ºC for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CHARGER PARAMETERS Deglitch time for battery short to VBAT rising or falling 1 ms fast charge transition Deglitch time for charge Both rising and falling, 2-mV over-drive, tRISE, tDGL(TERM) 32 ms termination tFALL=100ns tDGL(RCH) Deglitch time VBAT falling below VRCH, tFALL=100ns 32 ms Battery detection time (sourcing tDETECT(SRC) Termination enabled (TE = 1) 2 s current) Battery detection time (sinking tDETECT(SNK) Termination enabled (TE = 1) 250 ms current) INPUT TERMINALS (CD, PSEL) Deglitch for CD and PSEL CD or PSEL rising/falling 100 µs PROTECTION Deglitch time for supply rising tDGL(VSLP) Rising voltage, 2-mV over drive, tRISE=100ns 30 ms above VSLP+VSLP_EXIT tDGL(BOVP) BOVP Deglitch Battery entering/exiting BOVP 8 ms Safety Timer Accuracy –20% 20% BATTERY-PACK NTC MONITOR tDGL(TS) Deglitch time on TS change Applies to VHOT , VWARM , VCOOL , and VCOLD 50 ms I2C COMPATIBLE INTERFACE tWATCHDOG 30 50 s tI2CRESET 700 ms 7.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOSC Oscillator frequency 1.35 1.5 1.65 MHz DMAX Maximum duty cycle 95% DMIN Minimum duty cycle 0% Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: bq24187 Not Recommended for New Designs |
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