11

®

AFE1115

13.5dBm delivered to the line; and a pseudo-random

equiprobable sequence of HDSL pulses. The power dissipa-

tion specifications includes all power dissipated in the

AFE1115, it does not include power dissipated in the exter-

nal

load.

The external power is 16.5dBm, 13.5dBm to the line and

13.5dBm to the impedance matching resistors. The external

load power of 16.5dBm is 45mW. The typical power dissi-

pation in the AFE1115 under various conditions is shown in

TYPICAL POWER

BIT RATE

DISSIPATION

PER AFE1115

DVDD

IN THE AFE1115

(Symbols/sec)

(V)

(mW)

1168 (E1)

3.3

300

1168 (E1)

5

350

784 (T1)

3.3

290

784 (T1)

5

330

292 (1/4 E1)

3.3

280

292 (1/4 E1)

5

300

TABLE IV. Typical Power Dissipation.

Table IV.

LAYOUT

The analog front end of an HDSL system has a number of

conflicting requirements. It must accept and deliver digital

outputs at fairly high rates of speed, generate a VCXO clock,

phase-lock to a high-speed digital clock, and convert the line

input to a high-precision (14-bit) digital output. Thus, there

are really four sections of the AFE1115: the digital section,

the phase-locked loop, the VCXO and the analog section.

DIGITAL LAYOUT

The power supply for the digital section of the AFE1115 can

range from 3.3V to 5V. This supply should be decoupled to

digital ground with a ceramic 0.1

µF capacitor placed as

close as possible to digital ground (DGND, pin 16) and

supply plane and a digital ground plane should run to and

underneath the digital pins of the AFE1115 (pins 7 through

circuit board trance. A digital ground plane underneath all

digital pins is strongly recommended. The VCXO circuit

needs special attention for layout. There is a portion of the

external VCXO circuitry which needs to be as far away as

possible from a ground or power plane or other traces. See

the discussion below in the section titled VCXO Circuit and

Layout.

ANALOG LAYOUT

must be in the 4.75V to 5.25V range. This portion of the

AFE1115 should be decoupled with both 10

µF Tantalum

capacitor and a 0.1

µF ceramic capacitor. The ceramic ca-

pacitor should be placed as close to the AFE1115 as pos-

sible. The placement of the Tantalum capacitor is not as

critical, but should be close to the pin. In each case, the

(pins 49 and 50). The capacitors should be placed in quiet

analog areas rather than noisy digital areas.

10

Ω resistor should be used to connect PLL AV

to the analog supply. This resistor in combination with the

10

µF capacitor form a lowpass filter—keeping glitches on

the analog supply from affecting the phase locked loop.

Ideally, the phase-locked loop power supply would originate

from the analog supply (via the 5

Ω to 10Ω resistor) near the

power connector for the printed circuit board. Likewise, the

PLL ground should connect to a large PCB trace or small

ground plane which returns to the power supply connector

(pins 51 and 52).

The remaining portion of the AFE1115 should be considered

analog. The four non-PLL AGND pins (pins 36, 37, 42, and

46) should be connected directly to a common analog

ground plane and all non-PLL AV

nected to an analog 5V power plane. Both of these planes

should have a low impedance path to the power supply.

Ideally, all ground planes and traces and all power planes

and traces should return to the power supply connector

before being connected together (if necessary). Each ground

and power pair should be routed over each other, should not

overlap any portion of another pair, and the pairs should be

separated by a distance of at least 0.25 inch (6mm). One

exception is that the digital and analog ground planes should

be connected together underneath the AFE1115 by a small

trace.

VCXO CIRCUIT AND LAYOUT

The VCXO circuitry is shown in Figure 7. The basic VCXO

circuit consists of on-chip control DAC, amplifiers, Schmidt

triggers, and clock buffer along with an external crystal and

varactor diodes. The control DAC output (vcDAC) varies

the capacitance of the varactor diodes (D1 and D2), which

controls the frequency at which the crystal circuit oscillates.

The buffered clock output is available at pin 3, VCXO Clock

Output.

Important Note: To achieve specified analog performance

when using VCXO, the crystal frequency of the VCXO must

be 48x the baud rate. In addition, the txCLK and the

rxSYNC control signals must be derived from the VCXO

clock so that the edges of the control signal are synchronized

with the 48x crystal frequency. If these recommendations

are followed, the key internal analog decisions are made at

the time of minimum noise. As an example, for an E1 rate

of 1168kbps, the symbol rate is 584k symbols per second. In

this case the VCXO crystal frequency should be 48 x 584k

= 28.032MHz. Likewise, for T1, the crystal frequency should

be 18.816MHz.