DP83256 datasheet(3/144 Pages) NSC

Part #	DP83256

Description	PLAYERa??Device (FDDI Physical Layer Controller)

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Manufacturer	NSC [National Semiconductor (TI)]

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10 FDDI Chip Set Overview

National Semiconductor’s next generation FDDI 2-chip set

consists of two components as shown in

Figure 1-1 The

PLAYERa device integrates the features of the DP83231

CRDTM Clock Recovery Device DP83241 CDDTM Clock

Distribution Device and DP8325155 PLAYERTM Physical

Layer Controller In addition the PLAYERa device contains

enhanced SMT support

National Semiconductor’s FDDI TP-PMD Solutions consist

of two componentsthe DP83222 CYCLONETM Twisted

Pair FDDI Stream Cipher Device and the DP83223A

TWISTERTM Twisted Pair FDDI Transceiver Device

For more information on the other devices of the chip set

consult the appropriate datasheets and application notes

11 FDDI 2-CHIP SET

DP8325656-AP57 PLAYERa

Device Physical Layer Controller

The PLAYERa device implements the Physical Layer

(PHY) protocol as defined by the ANSI FDDI PHY X3T95

standard

Features

Y

Single chip FDDI Physical Layer (PHY) solution

Y

Integrated Digital Clock Recovery Module provides en-

hanced tracking and greater lock acquisition range

Y

Integrated Clock Generation Module provides all neces-

sary clock signals for an FDDI system from an external

125 MHz reference

Y

Alternate PMD Interface (DP83256-AP57) supports

UTP twisted pair FDDI PMDs with no external clock re-

covery or clock generation functions required

Y

No External Filter Components

Y

Connection Management (CMT) Support (LEM TNE

PC

React CF

React Auto Scrubbing)

Y

Full on-chip configuration switch

Y

Low Power CMOS-BIPOLAR design using a single 5V

supply

Y

Full duplex operation with through parity

Y

Separate management interface (Control Bus)

Y

Selectable Parity on PHY-MAC Interface and Control

Bus Interface

Y

Two levels of on-chip loopback

Y

4B5B encoderdecoder

Y

Framing logic

Y

Elasticity Buffer Repeat Filter and Smoother

Y

Line state detectorgenerator

Y

Supports single attach stations

dual attach stations

and concentrators with no external logic

Y

DP8325656-AP for SASDAS single path stations

Y

P83257 for SASDAS singledual path stations

In addition the DP83257 contains the additional PHY

Da-

tarequest and PHY

Dataindicate ports required for con-

centrators and dual attach dual path stations

DP83266 MACSITM Device Media

Access Controller and System

Interface

The DP83266 Media Access Controller and System Inter-

face (MACSI) implements the ANSI X3T95 Standard Media

Access Control (MAC) protocol for operation in an FDDI

token ring and provides a comprehensive System Interface

The MACSI device transmits receives repeats and strips

tokens and frames It produces and consumes optimized

data structures for efficient data transfer Full duplex archi-

tecture with through parity allows diagnostic transmission

and self testing for error isolation in point-to-point connec-

tions

The MACSI device includes the functionality of both the

DP83261 BMAC device and the DP83265 BSI-2 device with

additional enhancements for higher performance and reli-

ability

Features

Y

Over 9 Kbytes of on-chip FIFO

Y

5 DMA Channels (2 Output and 3 Input)

Y

125 MHz to 33 MHz operation

Y

Full duplex operation with through parity

Y

Real-time VOID frame stripping indicator for bridges

Y

On-chip Address bit swapping capability

Y

32-bit wide AddressData path with byte parity

Y

Programmable transfer burst sizes of 4 or 8 32-bit

words

Y

Receive frame filtering services

Y

Frame-per-Page mode controllable on each DMA

channel

Y

Demultiplexed Addresses supported on ABus

Y

New multicast address matching

Y

ANSI X3T95 MAC standard defined ring service op-

tions

Y

Supports all FDDI Ring Scheduling Classes (Synchro-

nous Asynchronous etc)

Y

Supports Individual Group Short Long and External

Addressing

Y

Generates Beacon Claim and Void frames

Y

Extensive ring and station statistics gathering

Y

Extension for MAC level bridging

Y

Enhanced SBus compatibility

Y

Interfaces to DRAMs or directly to system bus

Y

Supports frame HeaderInfo splitting

Y

Programmable Big or Little Endian alignment

3

Similar Part No. - DP83256

Manufacturer	Part #	Datasheet	Description
Texas Instruments	DP83256	1Mb / 146P	[Old version datasheet] PLAYER(TM) Device (FDDI Physical Layer Controller)
Texas Instruments	DP83256	1Mb / 146P	[Old version datasheet] PLAYER(TM) Device (FDDI Physical Layer Controller)

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National Semiconductor ...	DP83251	657Kb / 96P	PLAYER Device (FDDI Physical Layer Controller)
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DP83256 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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