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74AC11652DWR Datasheet(PDF) 3 Page - Texas Instruments |
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74AC11652DWR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 11 page 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS DATA I/O† OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8 OPERATION OR FUNCTION L H L L X X Input Input Isolation L H ↑↑ X X Input Input Store A and B data X H ↑ L X X Input Unspecified‡ Store A, hold B H H ↑↑ X‡ X Input Output Store A in both registers L XL ↑ X X Unspecified‡ Input Hold A, store B L L ↑↑ XX‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H L X H X Input Output Stored A data to B bus H L L L H H Output Output Stored A data to B bus and stored B data to A bus † The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. logic symbol§ ≥1 1 2 A1 2B1 1 4D 6D 1 7 26 OEBA 7 5 5 ≥1 EN1 [BA] 14 G7 27 SAB C4 28 CLKAB G5 15 SBA 16 CLKBA EN2 [AB] 1 OEAB C6 A2 3 B2 25 A3 4 B3 24 A4 5 B4 23 A5 10 B5 20 A6 11 B6 19 A7 12 B7 18 A8 13 B8 17 § This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. |
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