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ADS7890IPFBTG4 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS7890IPFBTG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 29 page ADS7890 SLAS409 − DECEMBER 2003 www.ti.com 9 Power Down Phase 12 3 4 5 PWD/RST BUSY SDO td6 tw4 First 4 Invalid Conversions Valid Conversions RESET Phase Invalid Data Valid Data td7 Figure 3. Device Power Down PWD/RST BUSY SDO tw3 First 4 Invalid Conversions Valid Conversions RESET Phase Invalid Data Valid Data td7 Figure 4. Device Reset FRAME ABORT A frame can be aborted at any time. There are three phases in the frame, data frame before sample start (first 8 clocks), sample phase (9th rising edge to the 16th falling edge of SCLK), and the conversion phase. The following sections describe a frame abort during each of these phases, for both SPI and DSP interfaces. FRAME ABORT IN SPI INTERFACE MODE (FS Held High) The rising edge of CS after a frame start (falling edge of CS) before the 9th rising edge of SCLK aborts a frame (see Figure 5). SDO goes to three-state with CS high. A new frame is started with the falling edge of CS. Previous conversion results are available on SDO during the new frame. D13 D12 D6 MSB-D13 LSB-D0 2 3 89 23 15 16 Data From Last Conversion SCLK CS BUSY SDO Figure 5. Frame Abort Before Sample Start A CS rising edge during the sample period (td8 after the 9th rising edge of SCLK to the 16th falling edge of SCLK) aborts the sample and the device enters the conversion phase. As expected, SDO goes to three-state with CS high. The conversion results can be latched in the next frame, however reliability of the data depends on the sampling time available before the frame abort. |
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