BQ24070RHLRG4 datasheet(5/33 Pages) TI1

Part #	BQ24070RHLRG4

Description	System Power-Path Management IC

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Manufacturer	TI1 [Texas Instruments]

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bq24070, bq24071

www.ti.com

SLUS694G – MARCH 2006 – REVISED DECEMBER 2014

7.4 Thermal Information

bq2407x

THERMAL METRIC(1)

RHL

UNIT

20 PINS

RθJA

Junction-to-ambient thermal resistance

40.1

RθJC(top)

Junction-to-case (top) thermal resistance

42.0

RθJB

Junction-to-board thermal resistance

16.6

°C/W

ψJT

Junction-to-top characterization parameter

0.7

ψJB

Junction-to-board characterization parameter

16.6

RθJC(bot)

Junction-to-case (bottom) thermal resistance

4.2

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over junction temperature range (0°C

≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT BIAS CURRENTS

ICC(SPLY)

Active supply current, VCC

VVCC > VVCC(min)

1

2

mA

VIN < V(BAT)

Sleep current (current into BAT

ICC(SLP)

2.6 V

≤ VI(BAT) ≤ VO(BAT-REG),

2

5

pin)

Excludes load on OUT pin

VI(IN) ≤ 6V, Total current into IN pin with chip

ICC(IN-STDBY)

Input standby current

disabled, Excludes all loads, CE=LOW, after

200

t(CE-HOLDOFF) delay

μA

Total current into BAT pin with input present

and chip disabled;

ICC(BAT-STDBY)

BAT standby current

Excludes all loads, CE=LOW,

45

65

after t(CE-HOLDOFF) delay,

0°C

≤ TJ ≤ 85°C

(1)

IIB(BAT)

Charge done current, BAT

Charge DONE, input supplying the load

1

5

OUT PIN-VOLTAGE REGULATION

bq24070

VI(IN) ≥ 4.4 V + VDO

4.4

4.5

Output regulation

VO(OUT-REG)

V

voltage

bq24071

VI(IN) ≥ 6 V + VDO

6.0

6.3

OUT PIN – DPPM REGULATION

V(DPPM-SET)

DPPM set point(2)

VDPPM-SET < VOUT

2.6

3.8

V

I(DPPM-SET)

DPPM current source

Input present

95

100

105

μA

SF

DPPM scale factor

V(DPPM-REG) = V(DPPM-SET) × SF

1.139

1.150

1.162

OUT PIN – FET (Q1, Q2) DROP-OUT VOLTAGE RDS(on))

VI(IN) ≥ VCC(min), Mode = High,

V(INDO)

IN-to-OUT dropout voltage(3)

300

475

II(IN) = 1 A, (IO(OUT)+ IO(BAT)), or no input

mV

BAT-to-OUT dropout voltage

V(BATDO)

VI (BAT) ≥ 3 V, II(BAT)= 1.0 A, VCC < VI(BAT)

40

100

(discharging)

(1)

This includes the quiescent current for the integrated LDO.

(2)

V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG).

(3)

VDO(max), dropout voltage is a function of the FET, RDS(on), and drain current. The dropout voltage increases proportionally to the

increase in current.

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