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BQ2014HSNTRG4 Datasheet(PDF) 9 Page - Texas Instruments |
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BQ2014HSNTRG4 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 28 page  Error Summary Capacity Inaccurate The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value in- cludes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated. (See the DCR description.) The other cause of LMD error is bat- tery wear-out. As the battery ages, the measured capac- ity must be adjusted to account for changes in actual battery capacity. A Capacity Inaccurate counter (CPI) is maintained and incremented each time a valid charge occurs (qualified by NAC; see the CPI register description). It is reset whenever LMD is updated from the DCR. The counter does not wrap around but stops counting at 255. The ca- pacity inaccurate flag (CI) is set if LMD has not been up- dated following 64 valid charges. Current-Sensing Error Table 6 shows the non-linearity and non-repeatability errors associated with the bq2014H current sensing. Table 7 illustrates the current-sensing error as a func- tion of VOS. A digital filter prevents charge and dis- charge counts to the NAC register when VSRO is be- tween VSRQ and VSRD. Done Input A charge-control IC or a microcontroller uses the DONE input to communicate charge status to the bq2014H. When the DONE input is asserted high on charge com- pletion, the bq2014H sets NAC = LMD and VDQ = 1. The DONE input should be maintained high as long as the charge controller or microcontroller keeps the bat- teries full; otherwise, the pin should be held low. Communicating with the bq2014H The bq2014H includes a simple single-pin (HDQ plus re- turn) serial data interface. A host processor uses the in- terface to access various bq2014H registers. Battery characteristics may be easily monitored by adding a sin- gle contact to the battery pack. The open-drain HDQ pin on the bq2014H should be pulled up by the host sys- tem, or may be left floating if the serial interface is not used. The interface uses a command-based protocol, in which the host processor sends a command byte to the bq2014H. The command directs the bq2014H to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte. (See Figure 4.) The communication protocol is asynchronous return-to- one. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 5K bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host proces- sors using either polled or interrupt processing. Data input from the bq2014H may be sampled using the pulse-width capture timers available on some microcon- trollers. If a communication error occurs (e.g., tCYCB > 250 µs), the bq2014H should be sent a BREAK to reinitiate the serial interface. A BREAK is detected when the HDQ pin is driven to a logic-low state for a time, tB or greater. The HDQ pin should then be returned to its normal ready-high logic state for a time, tBR. The bq2014H is now ready to receive a command from the host proces- sor. 9 VOS ( µV) Sense Resistor 20 50 100 m Ω 50 0.25 0.10 0.05 % 100 0.50 0.20 0.10 % 150 0.75 0.30 0.15 % 180 0.90 0.36 0.18 % Table 7. VOS-Related Current Sense Error (Current = 1A) Symbol Parameter Typical Maximum Units Notes INL Integrated non-linearity error ± 2 ± 4 % Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V. INR Integrated non- repeatability error ± 1 ± 2 % Measurement repeatability given similar operating conditions. Table 6. bq2014H Current-Sensing Errors bq2014H |
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