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BQ2011K Datasheet(PDF) 8 Page - Texas Instruments |
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BQ2011K Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 22 page  Self-Discharge Compensation The self-discharge compensation is programmed for a nominal rate of 1 80 * NAC per day or disabled. This is the rate for a battery within the 20–30°C temperature range (TMPGG = 6x). This rate varies across 8 ranges from <10°C to >70°C, doubling with each higher tem- perature step (10°C). See Table 3. Error Summary The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value in- cludes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated (see the DCR description in the “Layout Considerations” section). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be ad- justed to account for changes in actual battery capacity. Current-Sensing Error Table 4 illustrates the current-sensing error as a func- tion of VSR. A digital filter eliminates charge and discharge counts to the NAC register when VSRO (VSR + VOS) is between -400 µV and 500µV. Communicating With the bq2011K The bq2011K includes a simple single-pin (DQ plus re- turn) serial data interface. A host processor uses the in- terface to access various bq2011K registers. Battery char- acteristics may be easily monitored by adding a single con- tact to the battery pack. The open-drain DQ pin on the bq2011K should be pulled up by the host system, or may be left floating if the serial interface is not used. The interface uses a command-based protocol, where the host processor sends a command byte to the bq2011K. The command directs the bq2011K to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data speci- fied by the command byte. The communication protocol is asynchronous return-to- one. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 333 bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2011K may be sampled using the pulse-width capture timers available on some microcontrollers. Communication is normally initiated by the host proces- sor sending a BREAK command to the bq2011K. A BREAK is detected when the DQ pin is driven to a logic-low state for a time, tB or greater. The DQ pin should then be returned to its normal ready-high logic state for a time, tBR. The bq2011K is now ready to re- ceive a command from the host processor. The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2011K taking the DQ pin to a 8 bq2011K Temperature Range Self-Discharge Compensation Typical Rate/Day < 10°C NAC 320 10–20°C NAC 160 20–30°C NAC 80 30–40°C NAC 40 40–50°C NAC 20 50–60°C NAC 10 60–70°C NAC 5 > 70°C NAC 25 . Table 3. Self-Discharge Compensation Symbol Parameter Typical Maximum Units Notes INL Integrated non-linearity error ± 2 ± 4 % Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V. INR Integrated non- repeatability error ± 1 ± 2 % Measurement repeatability given similar operating conditions. Table 4. bq2011K Current-Sensing Errors |
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