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74LS273 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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74LS273 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 6 page Switching Characteristics VCC ea50V TA ea25 C CL e 15 pF Symbol Parameter DM54LS DM74LS Units RL e 2kX Min Max Min Max fmax Maximum Clock Frequency 30 30 MHz tPLH Propagation Delay 24 24 ns tPHL CP to Qn 24 24 tPLH Propagation Delay 27 27 ns MR to Qn Functional Description The ’LS273 is an 8-bit parallel register with a common Clock and common Master Reset When the MR input is LOW the Q outputs are LOW independent of the other inputs Infor- mation meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to- HIGH transition of the clock input Truth Table Inputs Outputs MR CP Dn Qn LX X L H L HH H L LL H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Logic Symbol TLF9825 – 2 VCC e Pin 20 GND e Pin 10 Logic Diagram TLF9825 – 3 3 |
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