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ADS821

10

SBAS040B

time-align it with the data created from the following quan-

tizer stages. This aligned data is fed into a digital error

correction circuit that can adjust the output data based on the

information found on the redundant bits. This technique gives

the ADS821 excellent differential linearity and ensures no

missing-codes at the 10-bit level.

The output data is available in Straight Offset Binary (SOB) or

Binary Two’s Complement (BTC) format.

THE ANALOG INPUT AND INTERNAL REFERENCE

The analog input of the ADS821 can be configured in various

ways and driven with different circuits, depending on the

nature of the signal and the level of performance desired. The

ADS821 has an internal reference that sets the full-scale

input range of the A/D converter. The differential input range

has each input centered around the common-mode of +2.25V,

with each of the two inputs having a full-scale range of +1.25V

to +3.25V. Since each input is 2Vp-p and 180

° out-of-phase

with the other, a 4V differential input signal to the quantizer

results. As shown in Figure 3, the positive full-scale reference

(REFT) and the negative full-scale reference (REFB) are

brought out for external bypassing. In addition, the common-

mode (CM) voltage may be used as a reference to provide the

appropriate offset for the driving circuitry. However, care must

be taken not to appreciably load this reference node. For

more information regarding external references, single-ended

inputs, and ADS821 drive circuits, refer to the applications

section.

•

For most applications, the clock duty should be set to

50%. For applications requiring no missing codes, how-

ever, a slight skew in the duty cycle will improve DNL

performance for conversion rates > 35MHz and input

frequencies < 2MHz (see Timing Diagram) in the SO

package. For the best performance in the SSOP pack-

age, the clock should be skewed under all input frequen-

cies with conversion rates > 35MHz. A possible method

for skewing the 50% duty cycle source is shown in Figure 4.

FIGURE 3. Internal Reference Structure.

CLOCK REQUIREMENTS

The CLK pin accepts a CMOS level clock input. Both the

rising and falling edges of the externally applied clock con-

trols the various interstage conversions in the pipeline. There-

fore, the clock signal’s jitter, rise-and-fall times and duty cycle

can affect conversion performance.

•

Low clock jitter is critical to SNR performance in fre-

quency-domain signal environments.

•

Clock rise and fall times should be as short as possible

(< 2ns for best performance).

FIGURE 4. Clock Skew Circuit.

DIGITAL OUTPUT DATA

The 10-bit output data is provided at CMOS logic levels. There

is a 6.5 clock cycle data latency from the start convert signal

to the valid output data. The standard output coding is Straight

Offset Binary where a full-scale input signal corresponds to all

“1’s” at the output. This condition is met with pin 19 LOW or

Floating due to an internal pull-down resistor. By applying a

high voltage to this pin, a BTC output will be provided where

the most significant bit is inverted. The digital outputs of the

(pin 18) with a logic HIGH. Normal operation is achieved with

pin 18 LOW or Floating due to internal pull-down resistors. This

function is provided for testability purposes and is not meant to

drive digital buses directly or be dynamically changed during

the conversion process.

OUTPUT CODE

SOB

BTC

PIN 19

PIN 19

FLOATING or LOW

HIGH

+FS (IN = +3.25V, IN = +1.25V)

1111111111

0111111111

+FS – 1LSB

1111111111

0111111111

+FS – 2LSB

1111111110

0111111110

+3/4 Full-Scale

1110000000

0110000000

+1/2 Full-Scale

1100000000

0100000000

+1/4 Full-Scale

1010000000

0010000000

+1LSB

1000000001

0000000001

Bipolar Zero (IN = IN = +2.25V)

1000000000

0000000000

–1LSB

0111111111

1111111111

–1/4 Full-Scale

0110000000

1110000000

–1/2 Full-Scale

0100000000

1100000000

–3/4 Full-Scale

0010000000

1010000000

–FS + 1LSB

0000000001

1000000001

–FS (IN = +1.25V, IN = +3.25V)

0000000000

1000000000

NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.

TABLE I. Coding Table for the ADS821.

+1.25V

+3.25V

2k

Ω

2k

Ω

0.1

µF

0.1

µF

+2.25V

REFT

REFB

CM

ADS821

To

Internal

Comparators

21

22

23

0.1

µF

R

V

2k

Ω

V

DD

0.1

µF

V

DD

CLK

OUT

CLK

IN

IC2

IC1

IC1, IC2 = ACT04

R