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ADS801U Datasheet(PDF) 3 Page - Texas Instruments |
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ADS801U Datasheet(HTML) 3 Page - Texas Instruments |
3 / 19 page ADS801 3 SBAS036B www.ti.com ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted. NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal ( ≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits. ADS800U PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS (Cont.) 2-Tone Intermodulation Distortion (IMD)(3) f = 4.4MHz and 4.5MHz (–7dBFS each tone) +25 °C –64 dBc Full –63 dBc Signal-to-Noise Ratio (SNR) f = 500kHz (–1dBFS input) +25 °C64 66 dB Full 61 64 dB f = 10MHz (–1dBFS input) +25 °C62 65 dB Full 58 64 dB Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (–1dBFS input) +25 °C63 66 dB Full 60 63 dB f = 10MHz (–1dBFS input) +25 °C56 59 dB Full 54 58 dB Differential Gain Error NTSC or PAL +25 °C 0.5 % Differential Phase Error NTSC or PAL +25 °C 0.1 degrees Aperture Delay Time +25 °C2 ns Aperture Jitter +25 °C 7 ps rms Over-Voltage Recovery Time(4) 1.5x Full-Scale Input +25 °C2 ns OUTPUTS Logic Family TTL/HCT Compatible CMOS Logic Coding Logic Selectable Falling Edge Logic Levels Logic LOW, Full 0 0.4 V CL = 15pF max Logic HIGH, Full +2.5 +VS V CL = 15pF max 3-State Enable Time 20 40 ns 3-State Disable Time Full 2 10 ns POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Operating Full +4.75 +5.0 +5.25 V Supply Current: +IS Operating +25 °C54 65 mA Operating Full 54 68 mA Power Consumption Operating +25 °C 270 325 mW Operating Full 270 340 mW Thermal Resistance, θ JA SO-28 75 °C/W |
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