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ADS1130IPWR Datasheet(PDF) 8 Page - Texas Instruments |
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ADS1130IPWR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 17 page  DRDY/DOUT 17 16 15 1 18 0 LSB MSB Data DataReady SCLK t DS t CONV t SCLK t PD NewDataReady t SCLK t HT t UPDATE ADS1130 SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012 www.ti.com DATA RETRIEVAL or else the data are overwritten. Avoid data retrieval during the update period (tUPDATE). To avoid having The ADS1130 continuously converts the analog input DRDY/DOUT remain in the state of the last bit, the 24 signal. To retrieve data, wait until DRDY/DOUT goes SCLKs may be applied to force DRDY/DOUT high. low, as shown in Figure 6. After DRDY/DOUT goes This technique is useful when a host controlling the low, begin shifting out the data by applying SCLKs. device is polling DRDY/DOUT to determine when Data are shifted out MSB first. It is not required to data are ready. Do not apply more than 24 SCLKs shift out all 18 bits of data, but the data must be during data retrieval. retrieved before new data are updated (within tCONV) Figure 6. Data Retrieval Timing SYMBOL DESCRIPTION MIN TYP MAX UNITS tDS DRDY/DOUT low to first SCLK rising edge 0 ns tSCLK SCLK positive or negative pulse width 100 ns tPD SCLK rising edge to new data bit valid: propagation delay 50 ns tHT SCLK rising edge to old data bit valid: hold time 0 ns tUPDATE Data updating: no readback allowed 39 μs SPEED = 1 12.5 ms tCONV Conversion time (1/data rate) SPEED = 0 100 ms 8 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Links: ADS1130 |
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