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ADS774KU Datasheet(PDF) 7 Page - Texas Instruments |
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ADS774KU Datasheet(HTML) 7 Page - Texas Instruments |
7 / 21 page ADS774 7 ® presented as 12-bit words. The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. Conversion is initiated by a HIGH-to-LOW transition of R/C. The three-state data output buffers are enabled when R/C is HIGH and STATUS is LOW. Thus, there are two possible modes of operation; data can be read with either a positive pulse on R/C, or a negative pulse on STATUS. In either case the R/C pulse must remain LOW for a minimum of 25ns. Figure 3 illustrates timing with an R/C pulse which goes LOW and returns HIGH during the conversion. In this case, the three-state outputs go to the high-impedance state in response to the falling edge of R/C and are enabled for external access of the data after completion of the conver- sion. Figure 4 illustrates the timing when a positive R/C pulse is used. In this mode the output data from the previous conver- sion is enabled during the time R/C is HIGH. A new conversion is started on the falling edge of R/C, and the three-state outputs return to the high-impedance state until the next occurrence of a HIGH R/C pulse. Timing specifica- tions for stand-alone operation are listed in Table IV. FULLY CONTROLLED OPERATION Conversion Length Conversion length (8-bit or 12-bit) is determined by the state of the A0 input, which is latched upon receipt of a conver- sion start transition (described below). If A 0 is latched HIGH, the conversion continues for 8 bits. The full 12-bit conversion will occur if A 0 is LOW. If all 12 bits are read FIGURE 2. Basic ±10V Operation. following an 8-bit conversion, the 4LSBs (DB0-DB3) will be LOW (logic 0). A0 is latched because it is also involved in enabling the output buffers. No other control inputs are latched. CONVERSION START The converter initiates a conversion based on a transition occurring on any of three logic inputs (CE, CS, and R/C) as shown in Table III. Conversion is initiated by the last of the three to reach the required state and thus all three may be dynamically controlled. If necessary, all three may change state simultaneously, and the nominal delay time is the same regardless of which input actually starts the conversion. If it is desired that a particular input establish the actual start of conversion, the other two should be stable a minimum of 50ns prior to the transition of the critical input. Timing relationships for start of conversion timing are illustrated in Figure 5. The specifications for timing are contained in Table V. The STATUS output indicates the current state of the con- verter by being in a high state only during conversion. During this time the three state output buffers remain in a high-impedance state, and therefore data cannot be read during conversion. During this period additional transitions of the three digital inputs which control conversion will be ignored, so that conversion cannot be prematurely termi- nated or restarted. However, if A0 changes state after the beginning of conversion, any additional start conversion transition will latch the new state of A0, possibly resulting in an incorrect conversion length (8 bits vs 12 bits) for that conversion. DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Status Output Convert Command ADS774 +5V 10µF (1) NC* 50 Ω 50 Ω +5V Leave Unconnected *Not internally connected NOTE: (1) Connect to GND or V EE for Emulation Mode. Connect to +5V for Control Mode. ±10V Analog Input |
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