Electronic Components Datasheet Search |
|
ADC08D502CIYB-NOPB Datasheet(PDF) 11 Page - Texas Instruments |
|
ADC08D502CIYB-NOPB Datasheet(HTML) 11 Page - Texas Instruments |
11 / 48 page ADC08D502 www.ti.com SNOSC85A – AUGUST 2012 – REVISED APRIL 2013 Converter Electrical Characteristics (continued) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (1) (2) Typical Limits Units Symbol Parameter Conditions (3) (3) (Limits) ANALOG OUTPUT CHARACTERISTICS 0.95 V (min) VCMO Common Mode Output Voltage 1.26 1.45 V (max) VA = 1.8V 0.60 V VCMO input threshold to set DC VCMO_LVL Coupling mode VA = 2.0V 0.66 V Common Mode Output Voltage TC VCMO TA = −40°C to +85°C 118 ppm/°C Temperature Coefficient CLOAD Maximum VCMO load Capacitance 80 pF VCMO 1.20 V (min) VBG Bandgap Reference Output Voltage IBG = ±100 µA 1.26 1.33 V (max) Bandgap Reference Voltage TC VBG TA = −40°C to +85°C, IBG = ±100 µA 28 ppm/°C Temperature Coefficient Maximum Bandgap Reference Load CLOAD VBG 80 pF Capacitance TEMPERATURE DIODE CHARACTERISTICS 192 µA vs. 12 µA, 71.23 mV TJ = 25°C ΔVBE Temperature Diode Voltage 192 µA vs. 12 µA, 85.54 mV TJ = 85°C CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Error Match 1 LSB Positive Full-Scale Error Match Zero offset selected in Control Register 1 LSB Negative Full-Scale Error Match Zero offset selected in Control Register 1 LSB Phase Matching (I, Q) FIN = 1.0 GHz < 1 Degree Crosstalk from I (Aggressor) to Q Aggressor = 867 MHz F.S. X-TALK −71 dB (Victim) Channel Victim = 100 MHz F.S. Crosstalk from Q (Aggressor) to I Aggressor = 867 MHz F.S. X-TALK -71 dB (Victim) Channel Victim = 100 MHz F.S. CLOCK INPUT CHARACTERISTICS 0.4 VP-P (min) Sine Wave Clock 0.6 2.0 VP-P (max) VID Differential Clock Input Level 0.4 VP-P (min) Square Wave Clock 0.6 2.0 VP-P (max) II Input Current VIN = 0 or VIN = VA ±1 µA Differential 0.02 pF CIN Input Capacitance (7) (8) Each input to ground 1.5 pF DIGITAL CONTROL PIN CHARACTERISTICS VIH Logic High Input Voltage (9) 0.85 x VA V (min) VIL Logic Low Input Voltage (9) 0.15 x VA V (max) CIN Input Capacitance (8) (10) Each input to ground 1.2 pF (7) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. (8) This parameter is specified by design and is not tested in production. (9) This parameter is specified by design and/or characterization and is not tested in production. (10) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC08D502 |
Similar Part No. - ADC08D502CIYB-NOPB |
|
Similar Description - ADC08D502CIYB-NOPB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |