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ADC121C021Q Datasheet(PDF) 3 Page - Texas Instruments |
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ADC121C021Q Datasheet(HTML) 3 Page - Texas Instruments |
3 / 44 page Snap Back GND D1 PIN V+ 2.1k 41.5k 41.5k Snap Back GND D1 PIN ADC121C021, ADC121C021Q, ADC121C027 www.ti.com SNAS415F – JANUARY 2008 – REVISED MARCH 2013 PIN DESCRIPTIONS Symbol Type Equivalent Circuit Description Power and unbuffered reference voltage. VA must be free of VA Supply noise and decoupled to GND. GND Ground Ground for all on-chip circuitry. VIN Analog Input See Figure 22 Analog input. This signal can range from GND to VA. Alert output. Can be configured as active high or active low. ALERT Digital Output This is an open drain data line that must be pulled to the supply (VA) with an external pull-up resistor. Serial Clock Input. SCL is used together with SDA to control the transfer of data in and out of the device. This is an open SCL Digital Input drain data line that must be pulled to the supply (VA) with an external pull-up resistor. Serial Data bi-directional connection. Data is clocked into or Digital out of the internal 16-bit register with SCL. This is an open SDA Input/Output drain data line that must be pulled to the supply (VA) with an external pull-up resistor. Tri-level Address Selection Input. Sets Bits A0 & A1 of the ADR0 7-bit slave address. (see Table 1) Digital Input, three levels Tri-level Address Selection Input. Sets Bits A2 & A3 of the ADR1 7-bit slave address. (see Table 1) Package Pinouts VA GND VIN ALERT SCL SDA ADR0 ADR1 ADC121C021, SOT 1 2 3 4 5 6 N/A N/A ADC121C027, SOT 1 2 3 N/A 5 6 4 N/A ADC121C021, VSSOP 5 7 4 2 1 8 3 6 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC121C021 ADC121C021Q ADC121C027 |
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