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ADC11DV200 Datasheet(PDF) 11 Page - Texas Instruments |
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ADC11DV200 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 30 page  VA AGND To Internal Circuitry I/O ADC11DV200 www.ti.com SNAS477A – APRIL 2009 – REVISED APRIL 2013 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (1) (2) Units Symbol Parameter Conditions Typical (3) Limits (Limits) LVDS OUTPUT MODE Maximum Clock Frequency 200 MHz (max) DCS On 65 Minimum Clock Frequency MHz (min) DCS Off 45 DCS On 1.5 tCH Clock High Time ns (min) DCS Off 2.4 DCS On 1.5 tCL Clock Low Time ns (min) DCS Off 2.4 5/5.5 tCONV Conversion Latency Clock Cycles (A/B) tODA Output Delay of CLK to A-Channel Data Relative to rising edge of CLK 2.7 1.46 ns (min) tODB Output Delay of CLK to B-Channel Data Relative to falling edge of CLK 2.7 1.46 ns (min) tSU Data Output Setup Time Relative to DRDY 1.2 0.7 ns (min) tH Data Output Hold Time Relative to DRDY 1.2 0.7 ns (min) tAD Aperture Delay 0.7 ns tAJ Aperture Jitter 0.3 ps rms tSKEW Data-Data Skew 20 470 ps CMOS OUTPUT MODE (4) Maximum Clock Frequency 170 MHz DCS On 65 Minimum Clock Frequency MHz DCS Off 25 DCS On 1.76 tCH Clock High Time ns DCS Off 2.82 DCS On 1.76 tCL ns DCS Off 2.82 tCONV Conversion Latency 5.5 Clock Cycles 3.15 ns (min) tOD Output Delay of CLK to DATA Relative to falling edge of CLK 4.5 5.81 ns (max) tSU Data Output Setup Time Relative to DRDY 2.5 1.79 ns (min) tH Data Output Hold Time Relative to DRDY 3.4 2.69 ns (min) tAD Aperture Delay 0.7 ns tAJ Aperture Jitter 0.3 ps rms (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above VA or below AGND. (2) With a full scale differential input of 1.5VP-P , the 11-bit LSB is 732.8µV. (3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. (4) CMOS Specifications are for FCLK = 170 MHz. Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC11DV200 |
Similar Part No. - ADC11DV200_15 |
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Similar Description - ADC11DV200_15 |
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