ADC11C125

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SNAS387C – MAY 2007 – REVISED APRIL 2013

ADC11C125 11-Bit, 125 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS Outputs

Check for Samples: ADC11C125

1

FEATURES

DESCRIPTION

The ADC11C125 is a high-performance CMOS

2

•

1.1 GHz Full Power Bandwidth

analog-to-digital

converter

capable

of

converting

•

Internal Sample-and-Hold Circuit

analog input signals into 11-Bit digital words at rates

•

Low Power Consumption

up to 125 Mega Samples Per Second (MSPS). This

converter uses a differential, pipelined architecture

•

Internal Precision 1.0V Reference

with digital error correction and an on-chip sample-

•

Single-Ended or Differential Clock Modes

and-hold circuit to minimize power consumption and

•

Clock Duty Cycle Stabilizer

the

external

component

count,

while

providing

excellent dynamic performance. A unique sample-

•

Dual +3.3V and +1.8V Supply Operation

and-hold stage yields a full-power bandwidth of 1.1

•

Power-Down and Sleep Modes

GHz. The ADC11C125 operates from dual +3.3V and

•

Offset Binary or 2's Complement Output Data

+1.8V power supplies and consumes 608 mW of

Format

power at 125 MSPS.

•

Pin-Compatible: ADC14155, ADC12C170,

The separate +1.8V supply for the digital output

ADC11C170

interface allows lower power operation with reduced

•

48-pin WQFN Package, (7x7x0.8mm, 0.5mm

noise. A power-down feature reduces the power

consumption to 5 mW while still allowing fast wake-up

Pin-Pitch)

time to full operation. In addition there is a sleep

feature which consumes 50 mW of power and has a

APPLICATIONS

faster wake-up time.

•

High IF Sampling Receivers

The differential inputs provide a full scale differential

•

Wireless Base Station Receivers

input swing equal to 2 times the reference voltage. A

•

Power Amplifier Linearization

stable 1.0V internal voltage reference is provided, or

the ADC11C125 can be operated with an external

•

Multi-Carrier, Multi-Mode Receivers

reference.

•

Test and Measurement Equipment

Clock mode (differential versus single-ended) and

•

Communications Instrumentation

output

data

format

(offset

binary

versus

2's

•

Radar Systems

complement)

are

pin-selectable.

A

duty

cycle

stabilizer maintains performance over a wide range of

KEY SPECIFICATIONS

input clock duty cycles.

•

Resolution 11 Bits

The

ADC11C125

is

pin

compatible

with

the

•

Conversion Rate 125 MSPS

ADC12C170 and the ADC14155.

•

It is available in a 48-lead WQFN package and

•

operates over the industrial temperature range of

−40°C to +85°C.

•

•

Full Power Bandwidth 1.1 GHz (typ)

•

Power Consumption 608 mW (typ)

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2

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PRODUCTION DATA information is current as of publication date.

Copyright © 2007–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.